sb/intel/i82801gx: Add common LPC decode code

Generic LPC decode ranges can now be set from the devicetree.

Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

43 files changed, 156 insertions, 338 deletions

diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
index 5ce28a27a9..137c8fc929 100644
--- a/src/mainboard/apple/macbook21/devicetree.cb
+++ b/src/mainboard/apple/macbook21/devicetree.cb
@@ -77,6 +77,10 @@ chip northbridge/intel/i945
 			register "c3_latency" = "0x23"
 			register "p_cnt_throttling_supported" = "1"
 
+			register "gen1_dec" = "0x000c0681"
+			register "gen2_dec" = "0x000c1641"
+			register "gen4_dec" = "0x001c0301"
+
 			device pci 1b.0 on # Audio Controller
 				subsystemid 0x8384 0x7680
 			end
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 34cd378839..aced71ce6a 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -27,114 +27,6 @@
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <southbridge/intel/common/pmclib.h>
 
-static void ich7_enable_lpc(void)
-{
-	/* Enable Serial IRQ */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
-
-	/* I/O Decode Ranges
-	 * X60:       0x0210 == 00000010 00010000
-	 * Macbook21: 0x0010 == 00000000 00010000
-	 * Bit 9:8    LPT Decode Range. This field determines which range to
-	 *            decode for the LPT Port.
-	 *            00 = 378h - 37Fh and 778h - 77Fh
-	 *            10 = 3BCh - 3BEh and 7BCh - 7BEh
-	 */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
-
-	/* LPC_EN--LPC I/F Enables Register
-	 * X60:       0x1f0d == 00011111 00001101
-	 * Macbook21: 0x3807 == 00111000 00000111
-	 * Bit 13     CNF2_LPC_EN -- R/W. Microcontroller Enable # 2.
-	 *            0 = Disable.
-	 *            1 = Enables the decoding of the I/O locations 4Eh and 4Fh
-	 *            to the LPC interface. This range is used for a
-	 *            microcontroller.
-	 * Bit 12     CNF1_LPC_EN -- R/W. Super I/O Enable.
-	 *            0 = Disable.
-	 *            1 = Enables the decoding of the I/O locations 2Eh and 2Fh
-	 *            to the LPC interface. This range is used for
-	 *            Super I/O devices.
-	 * Bit 11     MC_LPC_EN -- R/W. Microcontroller Enable # 1.
-	 *            0 = Disable.
-	 *            1 = Enables the decoding of the I/O locations 62h and 66h
-	 *            to the LPC interface. This range is used for a
-	 *            microcontroller.
-	 * Bit 10     KBC_LPC_EN -- R/W. Keyboard Enable.
-	 *            0 = Disable.
-	 *            1 = Enables the decoding of the I/O locations 60h and 64h
-	 *            to the LPC interface. This range is used for a
-	 *            microcontroller.
-	 * Bit 9      GAMEH_LPC_EN -- R/W. High Gameport Enable
-	 *            0 = Disable.
-	 *            1 = Enables the decoding of the I/O locations 208h to 20Fh
-	 *            to the LPC interface. This range is used for a gameport.
-	 * Bit 8      GAMEL_LPC_EN -- R/W. Low Gameport Enable
-	 *            0 = Disable.
-	 *            1 = Enables the decoding of the I/O locations 200h to 207h
-	 *            to the LPC interface. This range is used for a gameport.
-	 * Bit 3      FDD_LPC_EN -- R/W. Floppy Drive Enable
-	 *            0 = Disable.
-	 *            1 = Enables the decoding of the FDD range to the LPC
-	 *            interface. This range is selected in the LPC_FDD/LPT
-	 *            Decode Range Register (D31:F0:80h, bit 12).
-	 * Bit 2      LPT_LPC_EN -- R/W. Parallel Port Enable
-	 *            0 = Disable.
-	 *            1 = Enables the decoding of the LPT range to the LPC
-	 *            interface. This range is selected in the LPC_FDD/LPT
-	 *            Decode Range Register (D31:F0:80h, bit 9:8).
-	 * Bit 1      COMB_LPC_EN -- R/W. Com Port B Enable
-	 *            0 = Disable.
-	 *            1 = Enables the decoding of the COMB range to the LPC
-	 *            interface. This range is selected in the LPC_COM Decode
-	 *            Range Register (D31:F0:80h, bits 6:4).
-	 * Bit 0      COMA_LPC_EN -- R/W. Com Port A Enable
-	 *            0 = Disable.
-	 *            1 = Enables the decoding of the COMA range to the LPC
-	 *            interface. This range is selected in the LPC_COM Decode
-	 *            Range Register (D31:F0:80h, bits 3:2).
-	 */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
-			| CNF1_LPC_EN | MC_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
-			| COMA_LPC_EN);
-
-	/* GEN1_DEC, LPC Interface Generic Decode Range 1
-	 * X60:       0x1601 0x007c == 00000000 01111100 00010110 00000001
-	 * Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001
-	 * Bit 31:24  Reserved.
-	 * Bit 23:18  Generic I/O Decode Range Address[7:2] Mask: A `1' in any
-	 *            bit position indicates that any value in the corresponding
-	 *            address bit in a received cycle will be treated as a
-	 *            match. The corresponding bit in the Address field, below,
-	 *            is ignored. The mask is only provided for the lower 6 bits
-	 *            of the DWord address, allowing for decoding blocks up to
-	 *            256 bytes in size.
-	 * Bit 17:16  Reserved.
-	 * Bit 15:2   Generic I/O Decode Range 1 Base Address (GEN1_BASE). This
-	 *            address is aligned on a 128-byte boundary, and must have
-	 *            address lines 31:16 as 0. NOTE: The Intel ICH7 does not
-	 *            provide decode down to the word or byte level.
-	 * Bit 1      Reserved.
-	 * Bit 0      Generic Decode Range 1 Enable (GEN1_EN) -- R/W.
-	 *            0 = Disable.
-	 *            1 = Enable the GEN1 I/O range to be forwarded to the LPC
-	 *            I/F
-	 */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0681);
-
-	/* GEN2_DEC, LPC Interface Generic Decode Range 2
-	 * X60:       0x15e1 0x000c == 00000000 00001100 00010101 11100001
-	 * Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001
-	 */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c1641);
-
-	/* GEN4_DEC, LPC Interface Generic Decode Range 4
-	 * X60:       0x0000 0x0000
-	 * Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001
-	 */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x001c0301);
-}
-
 static void rcba_config(void)
 {
 	/* V0CTL Virtual Channel 0 Resource Control */
@@ -205,7 +97,7 @@ void mainboard_romstage_entry(void)
 
 	enable_lapic();
 
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 
 	/* Set up the console */
 	console_init();
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index 57d1ec2c2c..9de168c5e4 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -66,15 +66,6 @@ static void mb_lpc_setup(void)
 	ich7_setup_cir();
 }
 
-static void ich7_enable_lpc(void)
-{
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
-	/* Decode range */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN
-			| KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291);
-}
-
 void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
@@ -83,7 +74,7 @@ void mainboard_romstage_entry(void)
 	u8 s3_resume;
 
 	/* Set southbridge and Super I/O GPIOs. */
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 	mb_lpc_setup();
 
 	console_init();
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb
index acb8ac6702..b68aaa9fa7 100644
--- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb
+++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb
@@ -54,6 +54,8 @@ chip northbridge/intel/x4x		# Northbridge
 			register "sata_ports_implemented" = "0x3"
 			register "gpe0_en" = "0x440"
 
+			register "gen1_dec" = "0x000c0291" # Superio HWM
+
 			device pci 1b.0 on		# Audio
 				subsystemid 0x1849 0x3662
 			end
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb
index 805f2dac93..160d025ca7 100644
--- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb
+++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb
@@ -48,6 +48,8 @@ chip northbridge/intel/x4x		# Northbridge
 			register "ide_enable_primary" = "0x1"
 			register "gpe0_en" = "0x440"
 
+			register "gen1_dec" = "0x000c0291" # Superio HWM
+
 			device pci 1b.0 on		# Audio
 				subsystemid 0x1849 0x3662
 			end
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
index f4d1dc4291..0a8f27546d 100644
--- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
+++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
@@ -49,6 +49,8 @@ chip northbridge/intel/x4x		# Northbridge
 			register "sata_ports_implemented" = "0x3"
 			register "gpe0_en" = "0x440"
 
+			register "gen1_dec" = "0x000c0291" # Superio HWM
+
 			device pci 1b.0 on		# Audio
 				subsystemid 0x1849 0x3662
 			end
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb
index 2fd6e4f649..8119ced94c 100644
--- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb
+++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb
@@ -47,6 +47,8 @@ chip northbridge/intel/x4x		# Northbridge
 			register "sata_ports_implemented" = "0x3"
 			register "gpe0_en" = "0x440"
 
+			register "gen1_dec" = "0x000c0291" # Superio HWM
+
 			device pci 1b.0 on		# Audio
 				subsystemid 0x1849 0x3662
 			end
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb
index 5479faf3e9..e5e3cf9b90 100644
--- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb
+++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb
@@ -48,6 +48,8 @@ chip northbridge/intel/x4x		# Northbridge
 			register "ide_enable_primary" = "0x1"
 			register "gpe0_en" = "0x440"
 
+			register "gen1_dec" = "0x000c0291" # Superio HWM
+
 			device pci 1b.0 on		# Audio
 				subsystemid 0x1849 0x3662
 			end
diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb
index 972dc5dc1f..b5409a25bb 100644
--- a/src/mainboard/asus/p5gc-mx/devicetree.cb
+++ b/src/mainboard/asus/p5gc-mx/devicetree.cb
@@ -55,6 +55,9 @@ chip northbridge/intel/i945
 
 			register "p_cnt_throttling_supported" = "0"
 
+			# SuperIO Power Management Events
+			register "gen1_dec" = "0x00040291"
+
 			device pci 1b.0 on # High Definition Audio
 				ioapic_irq 2 INTA 0x10
 			end
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index 58dac6e71c..3287b76416 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -96,20 +96,6 @@ static u8 msr_get_fsb(void)
 	return fsbcfg;
 }
 
-static void ich7_enable_lpc(void)
-{
-	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
-	// Set COM1/COM2 decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
-	// Enable COM1
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN
-			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
-			| COMA_LPC_EN);
-	// Enable SuperIO Power Management Events
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00040291);
-}
-
 static void rcba_config(void)
 {
 	/* Enable IOAPIC */
@@ -156,7 +142,7 @@ void mainboard_romstage_entry(void)
 
 	enable_lapic();
 
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb
index bc023d24c9..5012f88605 100644
--- a/src/mainboard/asus/p5qpl-am/devicetree.cb
+++ b/src/mainboard/asus/p5qpl-am/devicetree.cb
@@ -45,6 +45,8 @@ chip northbridge/intel/x4x		# Northbridge
 			register "ide_enable_primary" = "0x1"
 			register "gpe0_en" = "0x04000440"
 
+			register "gen1_dec" = "0x00000295" # HWM
+
 			device pci 1b.0 on  end		# Audio
 			device pci 1c.0 on  end		# PCIe 1: PCIe x1 slot
 			device pci 1c.1 on		# PCIe 2: NIC
diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c
index 2836bf7941..4653b42267 100644
--- a/src/mainboard/asus/p5qpl-am/romstage.c
+++ b/src/mainboard/asus/p5qpl-am/romstage.c
@@ -143,19 +143,6 @@ static void mb_lpc_setup(void)
 	ich7_setup_cir();
 }
 
-static void ich7_enable_lpc(void)
-{
-	pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);
-	/* Fixed IO decode ranges */
-	pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
-	/* LPC enable devices */
-	pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
-			   | FDD_LPC_EN | LPT_LPC_EN
-			   | COMB_LPC_EN |  COMA_LPC_EN);
-	/* IO decode range: HWM on 0x295 */
-	pci_write_config32(LPC_DEV, 0x84, 0x000295);
-}
-
 void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
@@ -164,7 +151,7 @@ void mainboard_romstage_entry(void)
 	u8 s3_resume;
 
 	/* Set southbridge and Super I/O GPIOs. */
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 	mb_lpc_setup();
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb
index a611ee35c5..19d3e10cfb 100644
--- a/src/mainboard/foxconn/d41s/devicetree.cb
+++ b/src/mainboard/foxconn/d41s/devicetree.cb
@@ -43,6 +43,8 @@ chip northbridge/intel/pineview		# Northbridge
       register "sata_ports_implemented" = "0x3"
       register "gpe0_en" = "0x441"
 
+      register "gen1_dec" = "0x00fc0a01" # Environment Controller
+
       device pci 1b.0 on end		# Audio
       device pci 1c.0 on end		# PCIe 1
       device pci 1c.1 on		# PCIe 2 (NIC)
diff --git a/src/mainboard/foxconn/d41s/early_init.c b/src/mainboard/foxconn/d41s/early_init.c
index 6568d96139..ab1dae14ca 100644
--- a/src/mainboard/foxconn/d41s/early_init.c
+++ b/src/mainboard/foxconn/d41s/early_init.c
@@ -26,17 +26,6 @@
 
 void bootblock_mainboard_early_init(void)
 {
-	/* Disable Serial IRQ */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
-	/* Decode range */
-	pci_or_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
-			   | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
-			   | COMA_LPC_EN);
-
-	/* Environment Controller */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01);
-
 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 }
 
diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb
index b196e24961..270d1355f1 100644
--- a/src/mainboard/foxconn/g41s-k/devicetree.cb
+++ b/src/mainboard/foxconn/g41s-k/devicetree.cb
@@ -49,6 +49,8 @@ chip northbridge/intel/x4x		# Northbridge
 			register "ide_enable_secondary" = "0x0"
 			register "sata_ports_implemented" = "0x3"
 
+			register "gen1_dec" = "0x003c0a01" # Super I/O EC and GPIO
+
 			device pci 1b.0 on end		# Audio
 			device pci 1c.0 on end		# PCIe 1
 			device pci 1c.1 on		# PCIe 2 (NIC)
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c
index 01473c80fc..f423c11378 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/romstage.c
@@ -70,16 +70,6 @@ static void mb_lpc_setup(void)
 	ich7_setup_cir();
 }
 
-static void ich7_enable_lpc(void)
-{
-	pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
-	pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |
-			FDD_LPC_EN | COMB_LPC_EN | COMA_LPC_EN);
-
-	/* Decode 64 bytes at 0x0a00 to LPC for Super I/O EC and GPIO. */
-	pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01);
-}
-
 void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
@@ -94,7 +84,7 @@ void mainboard_romstage_entry(void)
 	u8 s3_resume;
 
 	/* Set up southbridge and Super I/O GPIOs. */
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 	mb_lpc_setup();
 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb
index 81ee9b17aa..e2001d91d1 100644
--- a/src/mainboard/getac/p470/devicetree.cb
+++ b/src/mainboard/getac/p470/devicetree.cb
@@ -62,6 +62,10 @@ chip northbridge/intel/i945
 			register "docking_supported" = "1"
 			register "p_cnt_throttling_supported" = "1"
 
+			register "gen1_dec" = "0x001c02e1"
+			register "gen2_dec" = "0x00fc0601"
+			register "gen3_dec" = "0x00040069"
+
 			device pci 1b.0 on end # High Definition Audio
 			device pci 1c.0 on end # PCIe port 1
 			device pci 1c.1 on end # PCIe port 2
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 6b5de90e74..e27194aab9 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -51,26 +51,17 @@ static void setup_special_ich7_gpios(void)
 	outl(gpios, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
 }
 
-static void ich7_enable_lpc(void)
+/* Override the default lpc decode ranges */
+static void mb_lpc_decode(void)
 {
 	int lpt_en = 0;
 	if (read_option(lpt, 0) != 0)
 		lpt_en = LPT_LPC_EN;
 
-	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
 	// decode range
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);
 	// decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
-			| MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN
-			| FDD_LPC_EN| lpt_en | COMB_LPC_EN | COMA_LPC_EN);
-	// Enable 0x02e0 - 0x2ff
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1);
-	// Enable 0x600 - 0x6ff
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601);
-	// Enable 0x68 - 0x6f
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069);
+	pci_update_config32(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en);
 }
 
 /* This box has two superios, so enabling serial becomes slightly excessive.
@@ -206,7 +197,8 @@ void mainboard_romstage_entry(void)
 
 	enable_lapic();
 
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
+	mb_lpc_decode();
 	early_superio_config();
 
 	/* Set up the console */
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
index f7e8ccc9a6..ff5d57b39f 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
@@ -79,6 +79,9 @@ chip northbridge/intel/i945
 
 			register "p_cnt_throttling_supported" = "0"
 
+			register "gen1_dec" = "0x000c0801" # ???
+			register "gen2_dec" = "0x00040291" # Environment Controller
+
 			device pci 1b.0 on # High Definition Audio
 				ioapic_irq 2 INTA 0x10
 			end
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index 3a2c86da87..9a9e9473e6 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -56,22 +56,6 @@ static void setup_sio(void)
 	ite_reg_write(EC_DEV, 0x30, 0xff); // Enable
 }
 
-static void ich7_enable_lpc(void)
-{
-	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
-	// Set COM1/COM2 decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0000);
-	// Enable COM1
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
-			| CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-			| COMA_LPC_EN);
-	// Enable SuperIO Power Management Events
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0801);
-	/* LPC decode range 2: Environment Controller */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00040291);
-}
-
 static void rcba_config(void)
 {
 	/* Enable IOAPIC */
@@ -115,7 +99,7 @@ void mainboard_romstage_entry(void)
 	int s3resume = 0, boot_mode = 0;
 	enable_lapic();
 
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 	/* Enable SuperIO PM */
 	setup_sio();
 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
index 7045dbf8e1..13da3e8704 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
@@ -50,6 +50,8 @@ chip northbridge/intel/x4x		# Northbridge
       register "sata_ports_implemented" = "0x3"
       register "gpe0_en" = "0x40"
 
+      register "gen2_dec" = "0x007c0291" # HWM
+
       device pci 1b.0 on		# Audio
         subsystemid 0x1458 0xa002
       end
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 8ba173eec6..fa69d122cb 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -98,19 +98,6 @@ static void mb_gpio_init(void)
 	ich7_setup_cir();
 }
 
-static void ich7_enable_lpc(void)
-{
-	/* Disable Serial IRQ */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00);
-	/* Decode range */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
-		CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | FDD_LPC_EN
-			| LPT_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
-
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291);
-}
-
 void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
@@ -119,7 +106,7 @@ void mainboard_romstage_entry(void)
 	u8 s3_resume;
 
 	/* Set southbridge and Super I/O GPIOs. */
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 	mb_gpio_init();
 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb
index 97f7a7b49d..78743bd453 100644
--- a/src/mainboard/ibase/mb899/devicetree.cb
+++ b/src/mainboard/ibase/mb899/devicetree.cb
@@ -39,6 +39,9 @@ chip northbridge/intel/i945
 			register "c3_latency" = "85"
 			register "p_cnt_throttling_supported" = "0"
 
+			register "gen1_dec" = "0x00fc0291"
+			register "gen4_dec" = "0x00000301"
+
 			#device pci 1b.0 on end # High Definition Audio
 			device pci 1c.0 on end # PCIe
 			device pci 1c.1 on end # PCIe
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 3b17e3b634..fd258af554 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -32,22 +32,6 @@
 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
 #define SUPERIO_DEV PNP_DEV(0x4e, 0)
 
-static void ich7_enable_lpc(void)
-{
-	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
-	// Set COM1/COM2 decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
-	// Enable COM1/COM2/KBD/SuperIO1+2
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
-			| CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN
-			| COMB_LPC_EN);
-	// Enable HWM at 0x290
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0291);
-	// io 0x300 decode
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301);
-}
-
 /* This box has one superio
  * Also set up the GPIOs from the beginning. This is the "no schematic
  * but safe anyways" method.
@@ -178,7 +162,7 @@ void mainboard_romstage_entry(void)
 
 	enable_lapic();
 
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 	early_superio_config_w83627ehg();
 
 	/* Set up the console */
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index c01465c4e7..7114a29a83 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -52,6 +52,8 @@ chip northbridge/intel/i945
 			register "c3_latency" = "85"
 			register "p_cnt_throttling_supported" = "0"
 
+			register "gen1_dec" = "0x0007c0681" # SuperIO Power Management
+
 			device pci 1b.0 on end # High Definition Audio
 			device pci 1c.0 on end # PCIe port 1
 			device pci 1c.1 off end # PCIe port 2
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index f0ae18823e..ba01379548 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -28,19 +28,6 @@
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1)
 #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME)
 
-static void ich7_enable_lpc(void)
-{
-	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
-	// Set COM1/COM2 decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
-	// Enable COM1
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
-			| FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
-	// Enable SuperIO Power Management Events
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c0681);
-}
-
 static void rcba_config(void)
 {
 	/* Set up virtual channel 0 */
@@ -98,7 +85,7 @@ void mainboard_romstage_entry(void)
 
 	enable_lapic();
 
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 	/* Enable SuperIO PM */
 	lpc47m15x_enable_serial(PME_DEV, 0x680);
 	lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb
index 295fbc4f38..c00e998bcc 100644
--- a/src/mainboard/intel/dg41wv/devicetree.cb
+++ b/src/mainboard/intel/dg41wv/devicetree.cb
@@ -65,6 +65,8 @@ chip northbridge/intel/x4x		# Northbridge
 			register "ide_enable_primary" = "0x1"
 			register "gpe0_en" = "0x440"
 
+			register "gen1_dec" = "0x00fc0a01" # HWM
+
 			device pci 1b.0 on		# Audio
 				subsystemid 0x8086 0x5756
 			end
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c
index a6969ad4d2..c0127b6c45 100644
--- a/src/mainboard/intel/dg41wv/romstage.c
+++ b/src/mainboard/intel/dg41wv/romstage.c
@@ -56,19 +56,6 @@ static void mb_lpc_setup(void)
 	ich7_setup_cir();
 }
 
-static void ich7_enable_lpc(void)
-{
-	pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);
-	/* Fixed IO decode ranges */
-	pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
-	/* LPC enable devices */
-	pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
-			   | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-			   | COMB_LPC_EN |  COMA_LPC_EN);
-	/* IO decode range: HWM on 0xa00 */
-	pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01);
-}
-
 void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
@@ -77,7 +64,7 @@ void mainboard_romstage_entry(void)
 	u8 s3_resume;
 
 	/* Set southbridge and Super I/O GPIOs. */
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 	mb_lpc_setup();
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb
index e2c0d88a0a..741c47b8f9 100644
--- a/src/mainboard/kontron/986lcd-m/devicetree.cb
+++ b/src/mainboard/kontron/986lcd-m/devicetree.cb
@@ -39,6 +39,11 @@ chip northbridge/intel/i945
 			register "c3_latency" = "85"
 			register "p_cnt_throttling_supported" = "0"
 
+			register "gen1_dec" = "0x00fc0a01" # HWM
+			register "gen2_dec" = "0x000403e9" # COM3
+			register "gen3_dec" = "0x000402e9" # COM4
+			register "gen4_dec" = "0x00000301" # ??
+
 			device pci 1b.0 on end # High Definition Audio
 			device pci 1c.0 on end # PCIe
 			device pci 1c.1 on end # PCIe
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 229e3594c8..cb01046010 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -34,28 +34,14 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
 
-static void ich7_enable_lpc(void)
+/* Override the default lpc decode ranges */
+static void mb_lpc_decode(void)
 {
 	int lpt_en = 0;
 	if (read_option(lpt, 0) != 0)
 		lpt_en = LPT_LPC_EN; /* enable LPT */
 
-	/* Enable Serial IRQ */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
-	/* Set COM1/COM2 decode range */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
-	/* Enable COM1/COM2/KBD/SuperIO1+2 */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,  CNF2_LPC_EN
-			| CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN
-			| COMB_LPC_EN | lpt_en);
-	/* Enable HWM at 0xa00 */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01);
-	/* COM3 decode */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000403e9);
-	/* COM4 decode */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x000402e9);
-	/* io 0x300 decode */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301);
+	pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en);
 }
 
 /* This box has two superios, so enabling serial becomes slightly excessive.
@@ -221,7 +207,8 @@ void mainboard_romstage_entry(void)
 
 	enable_lapic();
 
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
+	mb_lpc_decode();
 	early_superio_config_w83627thg();
 
 	/* Set up the console */
diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
index 70900eae2c..ada50f39ce 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -82,6 +82,10 @@ chip northbridge/intel/i945
 			register "docking_supported" = "1"
 			register "p_cnt_throttling_supported" = "1"
 
+			register "gen1_dec" = "0x007c1601"
+			register "gen2_dec" = "0x000c15e1"
+			register "gen3_dec" = "0x001c1681"
+
 			device pci 1b.0 on # Audio Controller
 				subsystemid 0x17aa 0x2010
 			end
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index b003de8926..ac78aae841 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -32,25 +32,11 @@
 #include <southbridge/intel/common/pmclib.h>
 #include "dock.h"
 
-static void ich7_enable_lpc(void)
+/* Override the default lpc decode ranges */
+static void mb_lpc_decode(void)
 {
-	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
 	// decode range
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210);
-	// decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-			| KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN
-			| LPT_LPC_EN | COMA_LPC_EN);
-
-	/* range 0x1600 - 0x167f */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601);
-
-	/* range 0x15e0 - 0x15ef */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1);
-
-	/* range 0x1680 - 0x169f */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681);
 }
 
 static void early_superio_config(void)
@@ -140,7 +126,8 @@ void mainboard_romstage_entry(void)
 
 	enable_lapic();
 
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
+	mb_lpc_decode();
 
 	/* We want early GPIO setup, to be able to detect legacy I/O module */
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb
index ace2bfbff2..5559f7dcfd 100644
--- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb
+++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb
@@ -46,6 +46,8 @@ chip northbridge/intel/x4x		# Northbridge
 			register "ide_enable_primary" = "0x1"
 			register "gpe0_en" = "0x440"
 
+			register "gen1_dec" = "0x00fc0a01"
+
 			device pci 1b.0 on end		# Audio
 			device pci 1c.0 on end		# PCIe 1
 			device pci 1c.1 on		# PCIe 2: NIC
diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
index 10889a9286..d632d9ddbf 100644
--- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c
+++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
@@ -42,18 +42,6 @@ static void mb_lpc_setup(void)
 	ich7_setup_cir();
 }
 
-static void ich7_enable_lpc(void)
-{
-	pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);
-	/* Fixed IO decode ranges */
-	pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
-	/* LPC enable devices */
-	pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
-			   | FDD_LPC_EN | LPT_LPC_EN |  COMA_LPC_EN);
-	/* IO decode range: HWM on 0xa00 */
-	pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01);
-}
-
 void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
@@ -62,7 +50,7 @@ void mainboard_romstage_entry(void)
 	u8 s3_resume;
 
 	/* Set southbridge and Super I/O GPIOs. */
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 	mb_lpc_setup();
 	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index b3d87ccb4b..1a914fd009 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -76,6 +76,10 @@ chip northbridge/intel/i945
 			register "docking_supported" = "1"
 			register "p_cnt_throttling_supported" = "1"
 
+			register "gen1_dec" = "0x007c1601"
+			register "gen2_dec" = "0x000c15e1"
+			register "gen3_dec" = "0x001c1681"
+
 			device pci 1b.0 on # Audio Controller
 				subsystemid 0x17aa 0x2010
 			end
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 34d8d7a435..1008bb0e22 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -33,24 +33,11 @@
 #include <southbridge/intel/common/pmclib.h>
 #include "dock.h"
 
-static void ich7_enable_lpc(void)
+/* Override the default lpc decode ranges */
+static void mb_lpc_decode(void)
 {
-	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
 	// decode range
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210);
-	// decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-			| KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN
-			| LPT_LPC_EN | COMA_LPC_EN);
-	/* range 0x1600 - 0x167f */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601);
-
-	/* range 0x15e0 - 0x15ef */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1);
-
-	/* range 0x1680 - 0x169f */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681);
 }
 
 static void early_superio_config(void)
@@ -144,7 +131,8 @@ void mainboard_romstage_entry(void)
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10);  /* 0x4c == GC */
 	setup_pch_gpios(&mainboard_gpio_map);
 
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
+	mb_lpc_decode();
 
 	dlpc_init();
 	/* dock_init initializes the DLPC switch on
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
index 0ceef6a2fd..5bce304335 100644
--- a/src/mainboard/roda/rk886ex/devicetree.cb
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -62,6 +62,10 @@ chip northbridge/intel/i945
 			register "ide_enable_primary" = "0x1"
 			register "ide_enable_secondary" = "0x0"
 
+			register "gen1_dec" = "0x001c02e1" # COM3, COM4
+			register "gen2_dec" = "0x00fc0601" # ??
+			register "gen3_dec" = "0x00040069" # EC decode ??
+
 			device pci 1b.0 off end # High Definition Audio
 			device pci 1c.0 on end # PCIe port 1
 			device pci 1c.1 off end # PCIe port 2
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index e7724e4485..019ec1b733 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -30,26 +30,16 @@
 #include <southbridge/intel/common/pmclib.h>
 #include "option_table.h"
 
-static void ich7_enable_lpc(void)
+/* Override the default lpc decode ranges */
+static void mb_lpc_decode(void)
 {
 	int lpt_en = 0;
 	if (read_option(lpt, 0) != 0)
 		lpt_en = LPT_LPC_EN; /* enable LPT */
 
-	/* Enable Serial IRQ */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
-	/* decode range */
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);
-	/* decode range */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
-			| MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN
-			| FDD_LPC_EN | lpt_en | COMB_LPC_EN | COMA_LPC_EN);
-	/* COM3 and COM4 decode? */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x1c02e1);
-	/* ??decode?? */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601);
-	/* EC decode? */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069);
+
+	pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en);
 }
 
 /* This box has two superios, so enabling serial becomes slightly excessive.
@@ -177,7 +167,8 @@ void mainboard_romstage_entry(void)
 
 	enable_lapic();
 
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
+	mb_lpc_decode();
 	early_superio_config();
 
 	/* Set up the console */
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc
index 2e9d31a3e8..31264295ad 100644
--- a/src/southbridge/intel/i82801gx/Makefile.inc
+++ b/src/southbridge/intel/i82801gx/Makefile.inc
@@ -15,6 +15,7 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y)
 
+bootblock-y += early_init.c
 bootblock-y += bootblock_gcc.c
 
 ramstage-y += i82801gx.c
@@ -34,6 +35,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
 smm-y += smihandler.c
 
+romstage-y += early_init.c
 romstage-y += early_smbus.c
 romstage-y += early_cir.c
 
diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c
index 996788888a..063a461e43 100644
--- a/src/southbridge/intel/i82801gx/bootblock_gcc.c
+++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c
@@ -41,4 +41,6 @@ void bootblock_early_southbridge_init(void)
 
 	/* Disable watchdog timer */
 	RCBA32(GCS) = RCBA32(GCS) | 0x20;
+
+	i82801gx_lpc_setup();
 }
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h
index 4e78c30db2..75b957573e 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -80,6 +80,12 @@ struct southbridge_intel_i82801gx_config {
 	int docking_supported:1;
 	int p_cnt_throttling_supported:1;
 	int c3_latency;
+
+	/* Additional LPC IO decode ranges */
+	uint32_t gen1_dec;
+	uint32_t gen2_dec;
+	uint32_t gen3_dec;
+	uint32_t gen4_dec;
 };
 
 #endif				/* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c
new file mode 100644
index 0000000000..533aaefe14
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/early_init.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci_ops.h>
+#include "i82801gx.h"
+#include "chip.h"
+
+void i82801gx_lpc_setup(void)
+{
+	const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
+	const struct device *dev = pcidev_on_root(0x1f, 0);
+	const struct southbridge_intel_i82801gx_config *config;
+
+	/* Configure serial IRQs.*/
+	pci_write_config8(d31f0, SERIRQ_CNTL, 0xd0);
+	/*
+	 * Enable some common LPC IO ranges:
+	 * - 0x2e/0x2f, 0x4e/0x4f often SuperIO
+	 * - 0x60/0x64, 0x62/0x66 often KBC/EC
+	 * - 0x3f0-0x3f5/0x3f7 FDD
+	 * - 0x378-0x37f and 0x778-0x77f LPT
+	 * - 0x2f8-0x2ff COMB
+	 * - 0x3f8-0x3ff COMA
+	 * - 0x208-0x20f GAMEH
+	 * - 0x200-0x207 GAMEL
+	 */
+	pci_write_config16(d31f0, LPC_IO_DEC, 0x0010);
+	pci_write_config16(d31f0, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
+			   | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
+			   | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+			   | COMB_LPC_EN | COMA_LPC_EN);
+
+	/* Set up generic decode ranges */
+	if (!dev || !dev->chip_info)
+		return;
+	config = dev->chip_info;
+
+	pci_write_config32(d31f0, GEN1_DEC, config->gen1_dec);
+	pci_write_config32(d31f0, GEN2_DEC, config->gen2_dec);
+	pci_write_config32(d31f0, GEN3_DEC, config->gen3_dec);
+	pci_write_config32(d31f0, GEN4_DEC, config->gen4_dec);
+}
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 8c85331af9..259fb49f54 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -40,6 +40,7 @@ void i82801gx_enable(struct device *dev);
 #endif
 
 void enable_smbus(void);
+void i82801gx_lpc_setup(void);
 
 #if ENV_ROMSTAGE
 int smbus_read_byte(unsigned int device, unsigned int address);