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authorRichard Spiegel <richard.spiegel@amd.corp-partner.google.com>2018-03-14 16:18:12 -0700
committerMartin Roth <martinroth@google.com>2018-03-16 19:01:30 +0000
commit013f1024c3f96ff9a59b70ae6a83ea3d7e9071dc (patch)
tree111fc11be71532229e362287216a3863c35b060d
parent0e0e93cce1a4707f169154d01478ac6faa1be771 (diff)
downloadcoreboot-013f1024c3f96ff9a59b70ae6a83ea3d7e9071dc.tar.xz
stoneyridge: Update AGESA binary and AGESA.h
AGESA.bin was updated in the binary repo, so update the submodule pointer. Among other changes, this added a callback "AGESA_HALT_THIS_AP", which requires updated header files. BUG=b:70338633 TEST=build kahlee. Change-Id: I5a07f1c539d00aed34cfe45d6d7ef60c1dc56566 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25183 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
m---------3rdparty/blobs0
-rw-r--r--src/vendorcode/amd/pi/00670F00/AGESA.h19
2 files changed, 19 insertions, 0 deletions
diff --git a/3rdparty/blobs b/3rdparty/blobs
-Subproject 19dea8d171544f01f12ee6b78af0cc356ab994a
+Subproject a4b561391f59e09059ce851fa19b64ca945672d
diff --git a/src/vendorcode/amd/pi/00670F00/AGESA.h b/src/vendorcode/amd/pi/00670F00/AGESA.h
index 17f69867d6..2b2a8b6b62 100644
--- a/src/vendorcode/amd/pi/00670F00/AGESA.h
+++ b/src/vendorcode/amd/pi/00670F00/AGESA.h
@@ -67,6 +67,7 @@
#define AGESA_RUNFUNC_ON_ALL_APS 0x00028106ul
#define AGESA_IDLE_AN_AP 0x00028107ul
#define AGESA_WAIT_FOR_ALL_APS 0x00028108ul
+#define AGESA_HALT_THIS_AP 0x00028109ul
// AGESA ADVANCED CALLOUTS, Memory
#define AGESA_READ_SPD 0x00028140ul
@@ -2514,6 +2515,18 @@ typedef struct {
IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference
} AGESA_READ_SPD_PARAMS;
+/// Parameters structure for the interface call-out AGESA_HALT_THIS_AP
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN BOOLEAN ExecWbinvd; ///< Indicates whether to execute
+ /// WBINVD
+ IN BOOLEAN PrimaryCore; ///< Indicates whether current core
+ /// is the primary core of the
+ /// compute unit
+ IN BOOLEAN CacheEn; ///< Indicates whether cache should
+ /// be enabled
+} AGESA_HALT_THIS_AP_PARAMS;
+
/// VoltageType values
typedef enum {
VTYPE_CPU_VREF, ///< Cpu side Vref
@@ -2625,6 +2638,12 @@ AgesaIdleAnAp (
);
AGESA_STATUS
+AgesaHaltThisAp (
+ IN UINTN FcnData,
+ IN AGESA_HALT_THIS_AP_PARAMS *HaltApParams
+);
+
+AGESA_STATUS
AgesaHookBeforeDramInit (
IN UINTN SocketIdModuleId,
IN OUT MEM_DATA_STRUCT *MemData