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authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-06-20 11:03:06 -0600
committerMartin Roth <martinroth@google.com>2019-08-09 20:23:50 +0000
commit0bd0806d2f8158cf43f52fc3106fc759bd6c4a94 (patch)
tree398a4c744b0018b6f8fc58c67cd43bd23842ec97
parentad1fdac9879eb0aba5d7f05752ae010f3bdcff66 (diff)
downloadcoreboot-0bd0806d2f8158cf43f52fc3106fc759bd6c4a94.tar.xz
soc/amd/picasso: Reduce 48M out configuration
Picasso has only a single 48M output. Simplify the setup function. Note that while the feature is similar to older products, the register definition and Enable bit has changed. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Iebaf5219fdcd3145a4faf906f656a7fbdc7e0c36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h3
-rw-r--r--src/soc/amd/picasso/southbridge.c18
2 files changed, 4 insertions, 17 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 36880a14a3..8c96aa7f99 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -175,6 +175,7 @@
#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT)
#define MISC_CLK_CNTL1 0x40
#define CG1PLL_FBDIV_TEST BIT(26)
+#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */
#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */
#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */
@@ -312,7 +313,7 @@ struct soc_power_reg {
};
void enable_aoac_devices(void);
-void sb_clk_output_48Mhz(u32 osc);
+void sb_clk_output_48Mhz(void);
void sb_disable_4dw_burst(void);
void sb_enable(struct device *dev);
void southbridge_final(void *chip_info);
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 84c15a7595..e1d16b7e3c 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -190,26 +190,12 @@ static void sb_enable_legacy_io(void)
pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN);
}
-void sb_clk_output_48Mhz(u32 osc)
+void sb_clk_output_48Mhz(void)
{
u32 ctrl;
- /*
- * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M)
- * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz.
- */
ctrl = misc_read32(MISC_CLK_CNTL1);
-
- switch (osc) {
- case 1:
- ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB;
- break;
- case 2:
- ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB;
- break;
- default:
- return; /* do nothing if invalid */
- }
+ ctrl |= BP_X48M0_OUTPUT_EN;
misc_write32(MISC_CLK_CNTL1, ctrl);
}