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authorLijian Zhao <lijian.zhao@intel.com>2017-09-14 16:25:18 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-11 17:26:07 +0000
commit0c8237aa0de9bd2c4a062b11f1f5dea414c2a845 (patch)
tree3618532e18ae50f0e980c52237d76d0a328ce730
parentbc37c678370ea0539ef90814bcf1cef50b42cb06 (diff)
downloadcoreboot-0c8237aa0de9bd2c4a062b11f1f5dea414c2a845.tar.xz
soc/intel/cannonlake: Change default UART number to 2
Set default UART number to 2 if 32bit PCI got selected, the proper debug print can be seen from serial port in case of switch between platforms, especially when change to lpss uart from legacy uart or vise versa. Change-Id: If2e0e8c8ac86e49a245f3d1d4722d40be9c01e25 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21544 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/cannonlake/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index b60d3d54a6..774fe41870 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -80,7 +80,7 @@ config UART_DEBUG
config UART_FOR_CONSOLE
int "Index for LPSS UART port to use for console"
- default 2 if DRIVERS_UART_8250MEM
+ default 2 if DRIVERS_UART_8250MEM_32
default 0
help
Index for LPSS UART port to use for console: