samus: Fix and clean up GPIOs and EC info/events

- Define specific GPIOs in gpio.h instaed of smihandler.c
- Add battery status event to SCI list
- Remove old proto board version defines and SPD index usage
- Do not disable cmd_pwr training now that it works on EVT board

BUG=chrome-os-partner:32196,chrome-os-partner:29117
BRANCH=samus
TEST=build and boot on samus

Change-Id: I50f1599aa4266ed61749cc7f4229a9384b498df2
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 0e3ebcb8659c92874d3ca89fa3a6795c9b6eebfa
Original-Change-Id: I53cf8d80ed7f675c10fa04e8fe8b879a4af9b21f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220321
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9220
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

6 files changed, 10 insertions, 26 deletions

diff --git a/src/mainboard/google/samus/ec.h b/src/mainboard/google/samus/ec.h
index 612d591bab..1ba16777ce 100644
--- a/src/mainboard/google/samus/ec.h
+++ b/src/mainboard/google/samus/ec.h
@@ -22,10 +22,6 @@
 
 #include <ec/google/chromeec/ec_commands.h>
 
-#define SAMUS_EC_BOARD_PROTO1_9 0
-#define SAMUS_EC_BOARD_PROTO2_A 1
-#define SAMUS_EC_BOARD_PROTO2_B 2
-
 #define EC_SCI_GPI  36   /* GPIO36 is EC_SCI# */
 #define EC_SMI_GPI  34   /* GPIO34 is EC_SMI# */
 
@@ -37,6 +33,7 @@
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD)  |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h
index df74a1aa0b..f293dee77e 100644
--- a/src/mainboard/google/samus/gpio.h
+++ b/src/mainboard/google/samus/gpio.h
@@ -24,6 +24,8 @@
 
 #define SAMUS_GPIO_PP3300_AUTOBAHN_EN	23
 #define SAMUS_GPIO_SSD_RESET_L		47
+#define SAMUS_GPIO_WLAN_DISABLE_L	42
+#define SAMUS_GPIO_LTE_DISABLE_L	59
 
 static const struct gpio_config mainboard_gpio_config[] = {
 	PCH_GPIO_UNUSED,        /* 0: UNUSED */
diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c
index ca43b81bf6..39a23f0b6a 100644
--- a/src/mainboard/google/samus/romstage.c
+++ b/src/mainboard/google/samus/romstage.c
@@ -56,13 +56,6 @@ void mainboard_romstage_entry(struct romstage_params *rp)
 	mainboard_fill_spd_data(&pei_data);
 	rp->pei_data = &pei_data;
 
-	/*
-	 * Disable use of PEI saved data to work around memory issues.
-	 */
-	if (cpu_family_model() == BROADWELL_FAMILY_ULT) {
-		pei_data.disable_cmd_pwr = 1;
-	}
-
 	/* Initalize memory */
 	romstage_common(rp);
 
diff --git a/src/mainboard/google/samus/smihandler.c b/src/mainboard/google/samus/smihandler.c
index 932d606ba0..a97f4269e4 100644
--- a/src/mainboard/google/samus/smihandler.c
+++ b/src/mainboard/google/samus/smihandler.c
@@ -31,10 +31,7 @@
 #include <broadwell/pm.h>
 #include <broadwell/smm.h>
 #include "ec.h"
-
-#define GPIO_SSD_RESET_L    47
-#define GPIO_WLAN_DISABLE_L 42
-#define GPIO_LTE_DISABLE_L  59
+#include "gpio.h"
 
 int mainboard_io_trap_handler(int smif)
 {
@@ -104,11 +101,11 @@ void mainboard_smi_sleep(u8 slp_typ)
 		}
 
 		/* Put SSD in reset to prevent leak. */
-		set_gpio(GPIO_SSD_RESET_L, 0);
+		set_gpio(SAMUS_GPIO_SSD_RESET_L, 0);
 		/* Prevent leak from standby rail to WLAN rail in S3. */
-		set_gpio(GPIO_WLAN_DISABLE_L, 0);
+		set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0);
 		/* Disable LTE */
-		set_gpio(GPIO_LTE_DISABLE_L, 0);
+		set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0);
 
 		/* Enable wake events */
 		google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
@@ -122,11 +119,11 @@ void mainboard_smi_sleep(u8 slp_typ)
 		}
 
 		/* Put SSD in reset to prevent leak. */
-		set_gpio(GPIO_SSD_RESET_L, 0);
+		set_gpio(SAMUS_GPIO_SSD_RESET_L, 0);
 		/* Prevent leak from standby rail to WLAN rail in S5. */
-		set_gpio(GPIO_WLAN_DISABLE_L, 0);
+		set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0);
 		/* Disable LTE */
-		set_gpio(GPIO_LTE_DISABLE_L, 0);
+		set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0);
 
 		/* Enable wake events */
 		google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
diff --git a/src/mainboard/google/samus/spd/spd.c b/src/mainboard/google/samus/spd/spd.c
index 00e694e9d2..0051fee333 100644
--- a/src/mainboard/google/samus/spd/spd.c
+++ b/src/mainboard/google/samus/spd/spd.c
@@ -93,10 +93,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 	int spd_file_len;
 	struct cbfs_file *spd_file;
 
-	/* Proto2B boards use a different GPIO for SPD index bit 3 */
-	if (google_chromeec_get_board_version() <= SAMUS_EC_BOARD_PROTO2_A)
-		spd_bits[3] = SPD_GPIO_BIT3_OLD;
-
 	spd_gpio[0] = get_gpio(spd_bits[0]);
 	spd_gpio[1] = get_gpio(spd_bits[1]);
 	spd_gpio[2] = get_gpio(spd_bits[2]);
diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h
index 4b2f3aab52..27d14691b7 100644
--- a/src/mainboard/google/samus/spd/spd.h
+++ b/src/mainboard/google/samus/spd/spd.h
@@ -37,7 +37,6 @@
 #define SPD_GPIO_BIT1		68
 #define SPD_GPIO_BIT2		67
 #define SPD_GPIO_BIT3		65
-#define SPD_GPIO_BIT3_OLD	66
 
 struct pei_data;
 void mainboard_fill_spd_data(struct pei_data *pei_data);