arch/arm/armv7: Fix coding style

Change-Id: Ib5d574347373009c8021597f555e6e86c2c0c41f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

4 files changed, 12 insertions, 12 deletions

diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S
index da7509da3b..e2d76a1463 100644
--- a/src/arch/arm/armv7/bootblock.S
+++ b/src/arch/arm/armv7/bootblock.S
@@ -89,11 +89,11 @@ call_bootblock:
 	/* Set stackpointer in internal RAM to call bootblock main() */
 	ldr	sp, =_estack
 	ldr	r0,=0x00000000
-	 /*
-	  * The current design of cpu_info places the struct at the top of the
-	  * stack. Free enough space to accommodate for that, but make sure it's
-	  * 8-byte aligned for ABI compliance.
-	  */
+	/*
+	 * The current design of cpu_info places the struct at the top of the
+	 * stack. Free enough space to accommodate for that, but make sure it's
+	 * 8-byte aligned for ABI compliance.
+	 */
 	sub	sp, sp, #16
 	bl	main
 
diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S
index 21a16d27ab..1f6cd5bc25 100644
--- a/src/arch/arm/armv7/cpu.S
+++ b/src/arch/arm/armv7/cpu.S
@@ -84,7 +84,7 @@
 	lsl	ip, ip, r2		@ shift by that into way position
 	mov	r0, #1
 	lsl	r2, r0, r2		@ r2 now contains the way decr
-	mov	r0, r3 			@ get sets/level (no way yet)
+	mov	r0, r3			@ get sets/level (no way yet)
 	orr	r3, r3, ip		@ merge way into way/set/level
 	bfc	r0, #0, #4		@ clear low 4 bits (level) to get numset - 1
 	sub	r2, r2, r0		@ subtract from way decr
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index 957b4b6a7c..935f778ec5 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -45,8 +45,8 @@
 #define ATTR_BLOCK (\
 	0ULL << 54 |	/* XN. 0:Not restricted */ \
 	0ULL << 53 |	/* PXN. 0:Not restricted */ \
-	1 << 10 |	/* AF. 1:Accessed. This is to prevent access \
-			 * fault when accessed for the first time */ \
+	1 << 10 |	/* AF. 1:Accessed. This is to prevent access */ \
+			/* fault when accessed for the first time */ \
 	0 << 6 |	/* AP[2:1]. 0b00:full access from PL1 */ \
 	0 << 5 |	/* NS. 0:Output address is in Secure space */ \
 	0 << 1 |	/* block/table. 0:block entry */ \
@@ -219,7 +219,7 @@ void mmu_config_range_kb(u32 start_kb, u32 size_kb, enum dcache_policy policy)
 	       start_kb * KiB, (start_kb + size_kb) * KiB, attrs[policy].name);
 
 	u32 end_kb = ALIGN_UP((start_kb + size_kb), PAGE_SIZE/KiB) -
-			(start_kb & ~mask);
+		     (start_kb & ~mask);
 
 	assert(end_kb <= BLOCK_SIZE/KiB);
 
@@ -285,7 +285,7 @@ void mmu_init(void)
 		int i;
 
 		printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n",
-			ttb_buff);
+		       ttb_buff);
 		ASSERT((read_mmfr0() & 0xf) >= 5);
 
 		/*
@@ -308,7 +308,7 @@ void mmu_init(void)
 		 */
 		for (i = 0; i < 4; i++) {
 			pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) |
-				ATTR_NEXTLEVEL;
+				      ATTR_NEXTLEVEL;
 			pmd += BLOCK_SIZE / PAGE_SIZE;
 		}
 
diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c
index 3b8d1af23e..751745b0c1 100644
--- a/src/arch/arm/armv7/thread.c
+++ b/src/arch/arm/armv7/thread.c
@@ -39,7 +39,7 @@ static inline uintptr_t push_stack(uintptr_t cur_stack, uintptr_t value)
 }
 
 void arch_prepare_thread(struct thread *t,
-			void asmlinkage(*thread_entry)(void *), void *arg)
+			 void asmlinkage(*thread_entry)(void *), void *arg)
 {
 	uintptr_t stack = t->stack_current;
 	int i;