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authorKyösti Mälkki <kyosti.malkki@gmail.com>2011-10-16 18:12:59 +0300
committerStefan Reinauer <stefan.reinauer@coreboot.org>2011-10-18 00:11:33 +0200
commit19fd2112f777054d9cfb4999ed9616d3460eaa76 (patch)
tree8cb3d42d8886b52fe84020ac0e54347d8e2d7609
parent521d8c25734dcfd38fa2e17a416e587fccb96080 (diff)
downloadcoreboot-19fd2112f777054d9cfb4999ed9616d3460eaa76.tar.xz
Append logical PME/GPIO device. Fix MPU device number.
A mainboard may require configuration of the superio pins to fully support some features. Things like A20# gate, leds, fans, infra-red and bootstrap jumpers may be configured and controlled through the logical PME device. Change-Id: I6e77ff0295806ba3dff339013f73d99c2961388f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/289 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/superio/smsc/lpc47m10x/lpc47m10x.h2
-rw-r--r--src/superio/smsc/lpc47m10x/superio.c1
2 files changed, 2 insertions, 1 deletions
diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x.h b/src/superio/smsc/lpc47m10x/lpc47m10x.h
index 4c78d9e632..535a4148cb 100644
--- a/src/superio/smsc/lpc47m10x/lpc47m10x.h
+++ b/src/superio/smsc/lpc47m10x/lpc47m10x.h
@@ -30,7 +30,7 @@
#define LPC47M10X2_KBC 7 /* Keyboard & Mouse */
#define LPC47M10X2_GAME 9 /* GAME */
#define LPC47M10X2_PME 10 /* PME reg*/
-#define LPC47M10X2_MPU 10 /* MPE -- who knows -- reg*/ // FIXME
+#define LPC47M10X2_MPU 11 /* MPU-401 MIDI */
#define LPC47M10X2_MAX_CONFIG_REGISTER 0x5F
diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c
index 0be8742e45..3d6a8ed1d7 100644
--- a/src/superio/smsc/lpc47m10x/superio.c
+++ b/src/superio/smsc/lpc47m10x/superio.c
@@ -65,6 +65,7 @@ static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
+ { &ops, LPC47M10X2_PME, PNP_IO0, { 0x0f80, 0 }, },
};
/**