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authorDavid Hendricks <dhendrix@chromium.org>2013-04-11 12:58:25 -0700
committerRonald G. Minnich <rminnich@gmail.com>2013-04-17 17:56:06 +0200
commit1a0b5e1c0594cb1bfe5094ad0c6eb183c9f3a593 (patch)
tree441e775fdf38e5659eb75a9ab11d3010d61fea16
parent130aafacb0998bddef222f1a4ae6e44003433279 (diff)
downloadcoreboot-1a0b5e1c0594cb1bfe5094ad0c6eb183c9f3a593.tar.xz
google/snow: enable 32KHz sleep clock
Change-Id: I9db91826e4534b8a6eea2b13bcf7c6abd848b4e4 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3075 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
-rw-r--r--src/mainboard/google/snow/romstage.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 4dce4398d8..41b88e1e5f 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -92,6 +92,8 @@ static int setup_pmic(void)
error |= max77686_volsetting(PMIC_BUS, PMIC_LDO10, CONFIG_VDD_LDO10_MV,
REG_ENABLE, MAX77686_MV);
+ error |= max77686_enable_32khz_cp(PMIC_BUS);
+
if (error)
printk(BIOS_CRIT, "%s: Error during PMIC setup\n", __func__);