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authorAamir Bohra <aamir.bohra@intel.com>2017-05-25 13:49:53 +0530
committerAaron Durbin <adurbin@chromium.org>2017-06-05 00:30:31 +0200
commit1fa16c9cb6c486cdd4b1bcb3734308b28b9c9a22 (patch)
tree3d29cd870fbf8345020361e70f3f19bd9c6b53bd
parent22b2c793e3587fb98d42f88e5e623621e055ff3a (diff)
downloadcoreboot-1fa16c9cb6c486cdd4b1bcb3734308b28b9c9a22.tar.xz
soc/intel/common: Add common Intel timer code
Add common timer code to get tsc frequency(Mhz). Change-Id: Ifd4b24735c74c636348fc32afbcc267e384cb610 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/common/block/timer/Kconfig4
-rw-r--r--src/soc/intel/common/block/timer/Makefile.inc6
-rw-r--r--src/soc/intel/common/block/timer/timer.c24
3 files changed, 34 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig
new file mode 100644
index 0000000000..a4150459aa
--- /dev/null
+++ b/src/soc/intel/common/block/timer/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_TIMER
+ bool
+ help
+ Intel Processor common TIMER support
diff --git a/src/soc/intel/common/block/timer/Makefile.inc b/src/soc/intel/common/block/timer/Makefile.inc
new file mode 100644
index 0000000000..b562c50781
--- /dev/null
+++ b/src/soc/intel/common/block/timer/Makefile.inc
@@ -0,0 +1,6 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c
+postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c
diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c
new file mode 100644
index 0000000000..12988856e4
--- /dev/null
+++ b/src/soc/intel/common/block/timer/timer.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <intelblocks/msr.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+ msr_t msr = rdmsr(MSR_PLATFORM_INFO);
+ return (CONFIG_CPU_BCLK_MHZ * ((msr.lo >> 8) & 0xff));
+}