soc/amd/stoneyridge: Add GNVS

Add ACPI asl for global non-volatile storage (GNVS).

Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

8 files changed, 214 insertions, 27 deletions

diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 416d4bdacf..f3c2b1b5d9 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -61,7 +61,7 @@ verstage-y += tsc_freq.c
 
 ramstage-y += chip.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += fixme.c
 ramstage-y += gpio.c
 ramstage-y += hda.c
diff --git a/src/soc/amd/stoneyridge/fadt.c b/src/soc/amd/stoneyridge/acpi.c
index f369651f06..fb97441da1 100644
--- a/src/soc/amd/stoneyridge/fadt.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -1,7 +1,8 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -20,21 +21,15 @@
 #include <string.h>
 #include <console/console.h>
 #include <arch/acpi.h>
+#include <arch/acpigen.h>
 #include <arch/io.h>
+#include <cbmem.h>
 #include <device/device.h>
+#include <soc/acpi.h>
 #include <soc/hudson.h>
+#include <soc/nvs.h>
 #include <soc/smi.h>
 
-#if IS_ENABLED(CONFIG_STONEYRIDGE_LEGACY_FREE)
-	#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
-#else
-	#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
-#endif
-
-#ifndef FADT_PM_PROFILE
-	#define FADT_PM_PROFILE PM_UNSPECIFIED
-#endif
-
 /*
  * Reference section 5.2.9 Fixed ACPI Description Table (FADT)
  * in the ACPI 3.0b specification.
@@ -205,3 +200,48 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 
 	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
 }
+
+unsigned long southbridge_write_acpi_tables(device_t device,
+		unsigned long current,
+		struct acpi_rsdp *rsdp)
+{
+	return acpi_write_hpet(device, current, rsdp);
+}
+
+static void acpi_create_gnvs(struct global_nvs_t *gnvs)
+{
+	/* Clear out GNVS. */
+	memset(gnvs, 0, sizeof(*gnvs));
+
+	if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))
+		gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
+
+	if (IS_ENABLED(CONFIG_CHROMEOS)) {
+		/* Initialize Verified Boot data */
+		chromeos_init_vboot(&gnvs->chromeos);
+		gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
+	}
+
+	/* Set unknown wake source */
+	gnvs->pm1i = ~0ULL;
+
+	/* CPU core count */
+	gnvs->pcnt = dev_count_cpu();
+}
+
+void southbridge_inject_dsdt(device_t device)
+{
+	struct global_nvs_t *gnvs;
+
+	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+
+	if (gnvs) {
+		acpi_create_gnvs(gnvs);
+		acpi_save_gnvs((uintptr_t)gnvs);
+
+		/* Add it to DSDT */
+		acpigen_write_scope("\\");
+		acpigen_write_name_dword("NVSA", (uintptr_t)gnvs);
+		acpigen_pop_len();
+	}
+}
diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl
index aae3287ba6..32dad76d56 100644
--- a/src/soc/amd/stoneyridge/acpi/cpu.asl
+++ b/src/soc/amd/stoneyridge/acpi/cpu.asl
@@ -13,14 +13,18 @@
  * GNU General Public License for more details.
  */
 
+/* Required function by EC, Notify OS to re-read CPU tables */
+Method (PNOT)
+{
+}
+
 /*
  * Processor Object
- *
  */
 Scope (\_PR) {		/* define processor scope */
 	Processor(
 		P000,		/* name space name */
-		0,			/* Unique number for this processor */
+		0,		/* Unique number for this processor */
 		0x810,		/* PBLK system I/O address !hardcoded! */
 		0x06		/* PBLKLEN for boot processor */
 		) {
@@ -28,49 +32,49 @@ Scope (\_PR) {		/* define processor scope */
 
 	Processor(
 		P001,		/* name space name */
-		1,			/* Unique number for this processor */
+		1,		/* Unique number for this processor */
 		0x0810,		/* PBLK system I/O address !hardcoded! */
 		0x06		/* PBLKLEN for boot processor */
 		) {
 	}
 	Processor(
 		P002,		/* name space name */
-		2,			/* Unique number for this processor */
+		2,		/* Unique number for this processor */
 		0x0810,		/* PBLK system I/O address !hardcoded! */
 		0x06		/* PBLKLEN for boot processor */
 		) {
 	}
 	Processor(
 		P003,		/* name space name */
-		3,			/* Unique number for this processor */
+		3,		/* Unique number for this processor */
 		0x0810,		/* PBLK system I/O address !hardcoded! */
 		0x06		/* PBLKLEN for boot processor */
 		) {
 	}
 	Processor(
 		P004,		/* name space name */
-		4,			/* Unique number for this processor */
+		4,		/* Unique number for this processor */
 		0x0810,		/* PBLK system I/O address !hardcoded! */
 		0x06		/* PBLKLEN for boot processor */
 		) {
 	}
 	Processor(
 		P005,		/* name space name */
-		5,			/* Unique number for this processor */
+		5,		/* Unique number for this processor */
 		0x0810,		/* PBLK system I/O address !hardcoded! */
 		0x06		/* PBLKLEN for boot processor */
 		) {
 	}
 	Processor(
 		P006,		/* name space name */
-		6,			/* Unique number for this processor */
+		6,		/* Unique number for this processor */
 		0x0810,		/* PBLK system I/O address !hardcoded! */
 		0x06		/* PBLKLEN for boot processor */
 		) {
 	}
 	Processor(
 		P007,		/* name space name */
-		7,			/* Unique number for this processor */
+		7,		/* Unique number for this processor */
 		0x0810,		/* PBLK system I/O address !hardcoded! */
 		0x06		/* PBLKLEN for boot processor */
 		) {
diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl
new file mode 100644
index 0000000000..bf0ed55249
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * NOTE: The layout of the GNVS structure below must match the layout in
+ * soc/amd/stoneyridge/include/soc/nvs.h !!!
+ *
+ */
+
+External (NVSA)
+
+OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+	/* Miscellaneous */
+	Offset (0x00),
+	PCNT,	8,      // 0x00 - Processor Count
+	PPCM,	8,      // 0x01 - Max PPC State
+	LIDS,	8,      // 0x02 - LID State
+	PWRS,	8,      // 0x03 - AC Power State
+	DPTE,	8,      // 0x04 - Enable DPTF
+	CBMC,	32,     // 0x05 - 0x08 - coreboot Memory Console
+	PM1I,	64,     // 0x09 - 0x10 - System Wake Source - PM1 Index
+	GPEI,	64,     // 0x11 - 0x18 - GPE Wake Source
+	NHLA,	64,     // 0x19 - 0x20 - NHLT Address
+	NHLL,	32,     // 0x21 - 0x24 - NHLT Length
+	PRT0,	32,     // 0x25 - 0x28 - PERST_0 Address
+	SCDP,	8,      // 0x29 - SD_CD GPIO portid
+	SCDO,	8,      // 0x2A - GPIO pad offset relative to the community
+	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
+	Offset (0x100),
+	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
+}
diff --git a/src/soc/amd/stoneyridge/acpi/lpc.asl b/src/soc/amd/stoneyridge/acpi/lpc.asl
index 783a2c952c..a41357a306 100644
--- a/src/soc/amd/stoneyridge/acpi/lpc.asl
+++ b/src/soc/amd/stoneyridge/acpi/lpc.asl
@@ -14,8 +14,9 @@
  */
 
 /* 0:14.3 - LPC */
-Device(LIBR) {
+Device(LPCB) {
 	Name(_ADR, 0x00140003)
+
 	/* Method(_INI) {
 	*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
 	} */ /* End Method(_SB.SBRDG._INI) */
@@ -37,7 +38,7 @@ Device(LIBR) {
 			)
 		})
 
-		Method(_CRS,0,NotSerialized)
+		Method(_CRS,0,Serialized)
 		{
 			CreateDwordField(^CRS,^BAR0._BAS,SPIB)	// Field to hold SPI base address
 			CreateDwordField(^CRS,^BAR0._LEN,SPIL)	// Field to hold SPI address length
@@ -100,4 +101,4 @@ Device(LIBR) {
 			IRQNoFlags(){13}
 		})
 	} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-} /* end LIBR */
+} /* end LPCB */
diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h
new file mode 100644
index 0000000000..f573b0ed81
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/acpi.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_STONEYRIDGE_ACPI_H_
+#define _SOC_STONEYRIDGE_ACPI_H_
+
+#include <arch/acpi.h>
+
+#if IS_ENABLED(CONFIG_STONEYRIDGE_LEGACY_FREE)
+	#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
+#else
+	#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
+#endif
+
+#ifndef FADT_PM_PROFILE
+	#define FADT_PM_PROFILE PM_UNSPECIFIED
+#endif
+
+unsigned long southbridge_write_acpi_tables(device_t device,
+		unsigned long current, struct acpi_rsdp *rsdp);
+
+void southbridge_inject_dsdt(device_t device);
+
+#endif	/* _SOC_STONEYRIDGE_ACPI_H_ */
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h
new file mode 100644
index 0000000000..b28f386ec8
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * NOTE: The layout of the global_nvs_t structure below must match the layout
+ * in soc/soc/amd/stoneyridge/acpi/globalnvs.asl !!!
+ *
+ */
+
+#ifndef _SOC_STONEYRIDGE_NVS_H_
+#define _SOC_STONEYRIDGE_NVS_H_
+
+#include <stdint.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+
+typedef struct global_nvs_t {
+	/* Miscellaneous */
+	uint8_t		pcnt; /* 0x00 - Processor Count */
+	uint8_t		ppcm; /* 0x01 - Max PPC State */
+	uint8_t		lids; /* 0x02 - LID State */
+	uint8_t		pwrs; /* 0x03 - AC Power State */
+	uint8_t		dpte; /* 0x04 - Enable DPTF */
+	uint32_t	cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
+	uint64_t	pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
+	uint64_t	gpei; /* 0x11 - 0x18 - GPE Wake Source */
+	uint64_t	nhla; /* 0x19 - 0x20 - NHLT Address */
+	uint32_t	nhll; /* 0x21 - 0x24 - NHLT Length */
+	uint32_t	prt0; /* 0x25 - 0x28 - PERST_0 Address */
+	uint8_t		scdp; /* 0x29 - SD_CD GPIO portid */
+	uint8_t		scdo; /* 0x2A - GPIO pad offset relative to the community */
+	uint8_t		unused[213];
+
+	/* ChromeOS specific (0x100 - 0xfff) */
+	chromeos_acpi_t chromeos;
+} __attribute__((packed)) global_nvs_t;
+
+#endif	/* _SOC_STONEYRIDGE_NVS_H_ */
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c
index d45ef0a416..fae5c554ba 100644
--- a/src/soc/amd/stoneyridge/lpc.c
+++ b/src/soc/amd/stoneyridge/lpc.c
@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <cbmem.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -28,8 +29,10 @@
 #include <arch/acpi.h>
 #include <pc80/i8254.h>
 #include <pc80/i8259.h>
+#include <soc/acpi.h>
 #include <soc/pci_devs.h>
 #include <soc/hudson.h>
+#include <soc/nvs.h>
 #include <vboot/vbnv.h>
 
 static void lpc_init(device_t dev)
@@ -105,6 +108,7 @@ static void lpc_init(device_t dev)
 static void hudson_lpc_read_resources(device_t dev)
 {
 	struct resource *res;
+	global_nvs_t *gnvs;
 
 	/* Get the normal pci resources of this device */
 	pci_dev_read_resources(dev);
@@ -132,6 +136,9 @@ static void hudson_lpc_read_resources(device_t dev)
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	compact_resources(dev);
+
+	/* Allocate ACPI NVS in CBMEM */
+	gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
 }
 
 static void hudson_lpc_set_resources(struct device *dev)
@@ -355,9 +362,8 @@ static struct device_operations lpc_ops = {
 	.read_resources = hudson_lpc_read_resources,
 	.set_resources = hudson_lpc_set_resources,
 	.enable_resources = hudson_lpc_enable_resources,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
-	.write_acpi_tables = acpi_write_hpet,
-#endif
+	.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+	.write_acpi_tables = southbridge_write_acpi_tables,
 	.init = lpc_init,
 	.scan_bus = scan_lpc_bus,
 	.ops_pci = &lops_pci,