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authorPaul Kocialkowski <contact@paulk.fr>2015-09-22 22:16:33 +0200
committerPatrick Georgi <pgeorgi@google.com>2016-03-23 21:12:31 +0100
commit263522db97b5b16d2408fa11c5c158f88539bc8c (patch)
tree79cc1e2b2c68b88e03aa20e92e19c0142e620f9e
parenteebe0e0db14476dde980896b8eb8a97129436af3 (diff)
downloadcoreboot-263522db97b5b16d2408fa11c5c158f88539bc8c.tar.xz
armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
As a follow up to Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede, use as builtin compiler hint instead of inline assembly to allow the compiler to generate more efficient code. Change-Id: I690514ac6d8988a6494ad3a77690709d932802b0 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/12083 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/arch/arm/include/armv7/arch/io.h21
1 files changed, 6 insertions, 15 deletions
diff --git a/src/arch/arm/include/armv7/arch/io.h b/src/arch/arm/include/armv7/arch/io.h
index 87797bd0eb..1772659fec 100644
--- a/src/arch/arm/include/armv7/arch/io.h
+++ b/src/arch/arm/include/armv7/arch/io.h
@@ -34,49 +34,40 @@
static inline uint8_t read8(const void *addr)
{
- uint8_t val;
-
dmb();
- asm volatile ("ldrb %0, [%1]" : "=r" (val) : "r" (addr) : "memory");
- return val;
+ return *(volatile uint8_t *)__builtin_assume_aligned(addr, sizeof(uint8_t));
}
static inline uint16_t read16(const void *addr)
{
- uint16_t val;
-
dmb();
- asm volatile ("ldrh %0, [%1]" : "=r" (val) : "r" (addr) : "memory");
- return val;
+ return *(volatile uint16_t *)__builtin_assume_aligned(addr, sizeof(uint16_t));
}
static inline uint32_t read32(const void *addr)
{
- uint32_t val;
-
dmb();
- asm volatile ("ldr %0, [%1]" : "=r" (val) : "r" (addr) : "memory");
- return val;
+ return *(volatile uint32_t *)__builtin_assume_aligned(addr, sizeof(uint32_t));
}
static inline void write8(void *addr, uint8_t val)
{
dmb();
- asm volatile ("strb %0, [%1]" : : "r" (val), "r" (addr) : "memory");
+ *(volatile uint8_t *)__builtin_assume_aligned(addr, sizeof(uint8_t)) = val;
dmb();
}
static inline void write16(void *addr, uint16_t val)
{
dmb();
- asm volatile ("strh %0, [%1]" : : "r" (val), "r" (addr) : "memory");
+ *(volatile uint16_t *)__builtin_assume_aligned(addr, sizeof(uint16_t)) = val;
dmb();
}
static inline void write32(void *addr, uint32_t val)
{
dmb();
- asm volatile ("str %0, [%1]" : : "r" (val), "r" (addr) : "memory");
+ *(volatile uint32_t *)__builtin_assume_aligned(addr, sizeof(uint32_t)) = val;
dmb();
}