src/cpu/amd/quadcore: Fix checkpatch errors/warnings

Fix over 80 character line warnings, unncessary braces for single
statement blocks warnings, include space before and after =, <, >
warnings, spaces after open parantheses warnings

Change-Id: Ib0a28c12e209547b3625f4ca1696f9c26dc2b6d0
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/19987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

3 files changed, 51 insertions, 37 deletions

diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
index a04ec558c0..129e025b7c 100644
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ b/src/cpu/amd/quadcore/amd_sibling.c
@@ -38,16 +38,15 @@ static u32 get_max_siblings(u32 nodes)
 {
 	device_t dev;
 	u32 nodeid;
-	u32 siblings=0;
+	u32 siblings = 0;
 
 	//get max siblings from all the nodes
-	for (nodeid=0; nodeid<nodes; nodeid++){
+	for (nodeid = 0; nodeid < nodes; nodeid++) {
 		int j;
 		dev = get_node_pci(nodeid, 3);
 		j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
-		if (siblings < j) {
+		if (siblings < j)
 			siblings = j;
-		}
 	}
 
 	return siblings;
@@ -60,7 +59,7 @@ static void enable_apic_ext_id(u32 nodes)
 	u32 nodeid;
 
 	//enable APIC_EXIT_ID all the nodes
-	for (nodeid=0; nodeid<nodes; nodeid++){
+	for (nodeid = 0; nodeid < nodes; nodeid++) {
 		u32 val;
 		dev = get_node_pci(nodeid, 0);
 		val = pci_read_config32(dev, 0x68);
@@ -82,9 +81,11 @@ u32 get_apicid_base(u32 ioapic_num)
 
 	siblings = get_max_siblings(sysconf.nodes);
 
-	if (sysconf.bsp_apicid > 0) { // IOAPIC could start from 0
+	if (sysconf.bsp_apicid > 0) {
+		// IOAPIC could start from 0
 		return 0;
-	} else if (sysconf.enabled_apic_ext_id)	{ // enabled ext id but bsp = 0
+	} else if (sysconf.enabled_apic_ext_id) {
+		// enabled ext id but bsp = 0
 		return 1;
 	}
 
@@ -93,7 +94,7 @@ u32 get_apicid_base(u32 ioapic_num)
 
 	//Construct apicid_base
 
-	if ((!disable_siblings) && (siblings>0) ) {
+	if ((!disable_siblings) && (siblings > 0)) {
 		/* for 8 way dual core, we will used up apicid 16:16, actually
 		   16 is not allowed by current kernel and the kernel will try
 		   to get one that is small than 16 to make IOAPIC work. I don't
@@ -101,14 +102,16 @@ u32 get_apicid_base(u32 ioapic_num)
 		   (APIC_EXT_ID is enabled) */
 
 		//4:10 for two way  8:12 for four way 16:16 for eight way
-		//Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency?
-		apicid_base = nb_cfg_54 ? (siblings+1) * sysconf.nodes :  8 * siblings + sysconf.nodes;
+		//Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes
+		//for better consistency?
+		apicid_base = nb_cfg_54 ? (siblings+1) * sysconf.nodes :
+				8 * siblings + sysconf.nodes;
 
 	} else {
 		apicid_base = sysconf.nodes;
 	}
 
-	if ((apicid_base+ioapic_num-1)>0xf) {
+	if ((apicid_base+ioapic_num-1) > 0xf) {
 		// We need to enable APIC EXT ID
 		printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n");
 		enable_apic_ext_id(sysconf.nodes);
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
index 097a88fcef..63b1384c40 100644
--- a/src/cpu/amd/quadcore/quadcore.c
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -2,7 +2,8 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
+ *	Raptor Engineering
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -34,9 +35,9 @@ u32 get_core_num_in_bsp(u32 nodeid)
 		dword >>= 12;
 		/* Bit 15 is CmpCap[2] since Revision D. */
 		if ((cpuid_ecx(0x80000008) & 0xff) > 3)
-	    	dword = ((dword & 8) >> 1) | (dword & 3);
+			dword = ((dword & 8) >> 1) | (dword & 3);
 		else
-	    	dword &= 3;
+			dword &= 3;
 	}
 	return dword;
 }
@@ -57,7 +58,8 @@ void real_start_other_core(uint32_t nodeid, uint32_t cores)
 	ssize_t i;
 	uint32_t dword;
 
-	printk(BIOS_DEBUG, "Start other core - nodeid: %02x  cores: %02x\n", nodeid, cores);
+	printk(BIOS_DEBUG,
+		"Start other core - nodeid: %02x  cores: %02x\n", nodeid, cores);
 
 	/* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4
 	   accesses and error logging to core0 */
@@ -72,15 +74,16 @@ void real_start_other_core(uint32_t nodeid, uint32_t cores)
 		uint32_t core_activation_flags = 0;
 		uint32_t active_cores = 0;
 
-		/* Set PCI_DEV(0, 0x18+nodeid, 0), 0x1dc bits 7:1 to start cores */
+		/* Set PCI_DEV(0, 0x18+nodeid, 0),
+		 * 0x1dc bits 7:1 to start cores
+		 */
 		dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x1dc);
-		for (i = 1; i < cores + 1; i++) {
+		for (i = 1; i < cores + 1; i++)
 			core_activation_flags |= 1 << i;
-		}
-
 		/* Start the first core of each compute unit */
 		active_cores |= core_activation_flags & 0x55;
-		pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword | active_cores);
+		pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword
+				  | active_cores);
 
 		/* Each core shares a single set of MTRR registers with
 		 * another core in the same compute unit, therefore, it
@@ -93,14 +96,17 @@ void real_start_other_core(uint32_t nodeid, uint32_t cores)
 		uint32_t timeout;
 		for (i = 1; i < cores + 1; i++) {
 			if (!(i & 0x1)) {
-				uint32_t ap_apicid = get_boot_apic_id(nodeid, i);
-				timeout = wait_cpu_state(ap_apicid, F10_APSTATE_ASLEEP, F10_APSTATE_ASLEEP);
+				uint32_t ap_apicid =
+				get_boot_apic_id(nodeid, i);
+				timeout = wait_cpu_state(ap_apicid,
+							F10_APSTATE_ASLEEP, F10_APSTATE_ASLEEP);
 			}
 		}
 
 		/* Start the second core of each compute unit */
 		active_cores |= core_activation_flags & 0xaa;
-		pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword | active_cores);
+		pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword |
+				   active_cores);
 	} else {
 		// set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
 		dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x68);
@@ -109,9 +115,8 @@ void real_start_other_core(uint32_t nodeid, uint32_t cores)
 
 		if (cores > 1) {
 			dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168);
-			for (i = 0; i < cores - 1; i++) {
+			for (i = 0; i < cores - 1; i++)
 				dword |= 1 << i;
-			}
 			pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword);
 		}
 	}
@@ -134,10 +139,10 @@ static void start_other_cores(void)
 
 	for (nodeid = 0; nodeid < nodes; nodeid++) {
 		u32 cores = get_core_num_in_bsp(nodeid);
-		printk(BIOS_DEBUG, "init node: %02x  cores: %02x pass 1\n", nodeid, cores);
-		if (cores > 0) {
+		printk(BIOS_DEBUG, "init node: %02x  cores: %02x pass 1\n",
+			nodeid, cores);
+		if (cores > 0)
 			real_start_other_core(nodeid, cores);
-		}
 	}
 }
 #endif
diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
index 9892c12347..47d9be9e6f 100644
--- a/src/cpu/amd/quadcore/quadcore_id.c
+++ b/src/cpu/amd/quadcore/quadcore_id.c
@@ -1,7 +1,8 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
+ *		      Raptor Engineering
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -26,12 +27,12 @@ u32 read_nb_cfg_54(void)
 {
 	msr_t msr;
 	msr = rdmsr(NB_CFG_MSR);
-	return ( ( msr.hi >> (54-32)) & 1);
+	return (msr.hi >> (54-32)) & 1;
 }
 
 u32 get_initial_apicid(void)
 {
-	return ((cpuid_ebx(1) >> 24) & 0xff);
+	return (cpuid_ebx(1) >> 24) & 0xff;
 }
 
 /* Called by amd_siblings (ramstage) as well */
@@ -75,7 +76,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
 	 * The apicid format varies based on processor revision
 	 */
 	apicid = (cpuid_ebx(1) >> 24) & 0xff;
-	if ( nb_cfg_54) {
+	if (nb_cfg_54) {
 		if (fam15h && dual_node) {
 			id.coreid = apicid & 0x1f;
 			id.nodeid = (apicid & 0x60) >> 5;
@@ -105,8 +106,10 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
 		}
 	}
 	if (fam15h && dual_node) {
-		/* coreboot expects each separate processor die to be on a different nodeid.
-		 * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed...
+		/* coreboot expects each separate processor die to be on a
+		 * different nodeid.
+		 * Since the code above returns nodeid 0 even on
+		 * internal node 1 some fixup is needed...
 		 */
 		uint32_t f5x84;
 		uint8_t core_count;
@@ -123,10 +126,13 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
 			id.coreid = id.coreid - core_count;
 		}
 	} else if (rev_gte_d && dual_node) {
-		/* coreboot expects each separate processor die to be on a different nodeid.
-		 * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed...
+		/* coreboot expects each separate processor die to be on a
+		 * different nodeid.
+		 * Since the code above returns nodeid 0 even on
+		 * internal node 1 some fixup is needed...
 		 */
-		uint8_t core_count = (((f3xe8 & 0x00008000) >> 13) | ((f3xe8 & 0x00003000) >> 12)) + 1;
+		uint8_t core_count = (((f3xe8 & 0x00008000) >> 13) |
+				     ((f3xe8 & 0x00003000) >> 12)) + 1;
 
 		id.nodeid = id.nodeid * 2;
 		if (id.coreid >= core_count) {