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| author | Peter Stuge <peter@stuge.se> | 2008-12-22 14:12:08 +0000 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2008-12-22 14:12:08 +0000 |
| commit | 3071acf37091e7217f153f993a27de936061088a (patch) | |
| tree | ecdddc2f380711e4cf1c223fea3169e5551cf2f2 | |
| parent | 93159bf752577365e10913257a9edc8d57990a8b (diff) | |
| download | coreboot-3071acf37091e7217f153f993a27de936061088a.tar.xz | |
flashrom: Initialize ICH SPI opcodes also for ICH9 and later.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | util/flashrom/chipset_enable.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/util/flashrom/chipset_enable.c b/util/flashrom/chipset_enable.c index b5af401078..00959ea5ad 100644 --- a/util/flashrom/chipset_enable.c +++ b/util/flashrom/chipset_enable.c @@ -384,6 +384,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, *(uint32_t *) (spibar + 0xA0)); ICH10 only? */ printf_debug("0xB0: 0x%08x (FDOC)\n", *(uint32_t *) (spibar + 0xB0)); + ich_init_opcodes(); break; default: /* Nothing */ |