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authorDuncan Laurie <dlaurie@chromium.org>2012-09-09 20:12:32 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-09 19:03:02 +0100
commit312ee0ca7096cdb35fe53e4b5e3285509e93bc68 (patch)
treef5118360a490ea982ac1179e771a81518fbc3c31
parent8e7d7fd4bf3bf0a0387af7616d739ec4aba9b1f0 (diff)
downloadcoreboot-312ee0ca7096cdb35fe53e4b5e3285509e93bc68.tar.xz
SPI: re-init SMM SPI driver after lockdown
If the driver is initialized before the lockdown then it will fail to work after the lockdown bit is set. Change-Id: Idc05d33d8d726bf29cb3c9b1b4604522bd64170a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1745 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/southbridge/intel/bd82x6x/finalize.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index ed1ebf7a9a..d50c8e6654 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -22,6 +22,7 @@
#include <arch/romcc_io.h>
#include <northbridge/intel/sandybridge/pcie_config.c>
#include "pch.h"
+#include "spi.h"
void intel_pch_finalize_smm(void)
{
@@ -34,6 +35,11 @@ void intel_pch_finalize_smm(void)
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
+#if CONFIG_SPI_FLASH_SMM
+ /* Re-init SPI driver to handle locked BAR */
+ spi_init();
+#endif
+
/* TCLOCKDN: TC Lockdown */
RCBA32_OR(0x0050, (1 << 31));