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authorElyes HAOUAS <ehaouas@noos.fr>2018-09-26 18:21:48 +0200
committerWerner Zeh <werner.zeh@siemens.com>2018-10-01 04:15:30 +0000
commit339ae162b6a666d558c49a6794966f5e339e76e7 (patch)
tree877e378f8b210f685f1fdd6d89cd3e01f5b9b2ad
parent1e67f0773bff13b6ced9e9cf101917538f49c48b (diff)
downloadcoreboot-339ae162b6a666d558c49a6794966f5e339e76e7.tar.xz
soc/intel/fsp_broadwell_de: Fix IA32_MC0_* names
Regarding the SDMs, IA32_MC0_STATUS register is at 0x401, and IA32_MC0_CTL is at 0x400. So replace MSR at (0x400+1) by IA32_MC0_STATUS and the one at 0x400 by IA32_MC0_CTL. Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
-rw-r--r--src/soc/intel/fsp_broadwell_de/cpu.c11
-rw-r--r--src/soc/intel/fsp_broadwell_de/include/soc/msr.h4
2 files changed, 8 insertions, 7 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c
index a50c839899..0b933c5db7 100644
--- a/src/soc/intel/fsp_broadwell_de/cpu.c
+++ b/src/soc/intel/fsp_broadwell_de/cpu.c
@@ -128,11 +128,10 @@ void broadwell_de_init_cpus(struct device *dev)
static void configure_mca(void)
{
msr_t msr;
- const unsigned int mcg_cap_msr = 0x179;
int i;
int num_banks;
- msr = rdmsr(mcg_cap_msr);
+ msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & 0xff;
/* TODO(adurbin): This should only be done on a cold boot. Also, some
@@ -140,14 +139,14 @@ static void configure_mca(void)
every bank. */
msr.lo = msr.hi = 0;
for (i = 0; i < num_banks; i++) {
- wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 1, msr);
- wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 2, msr);
- wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 3, msr);
+ wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC0_STATUS + (i * 4) + 1, msr);
+ wrmsr(IA32_MC0_STATUS + (i * 4) + 2, msr);
}
msr.lo = msr.hi = 0xffffffff;
for (i = 0; i < num_banks; i++)
- wrmsr(MSR_IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC0_CTL + (i * 4), msr);
}
static void broadwell_de_core_init(struct device *cpu)
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
index 6b87061109..ffa33da4b2 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
@@ -21,9 +21,11 @@
#define MSR_IA32_PLATFORM_ID 0x17
#define MSR_CORE_THREAD_COUNT 0x35
#define MSR_PLATFORM_INFO 0xce
+#define IA32_MCG_CAP 0x179
#define IA32_PERF_CTL 0x199
#define MSR_TURBO_RATIO_LIMIT 0x1ad
-#define MSR_IA32_MC0_STATUS 0x400
+#define IA32_MC0_CTL 0x400
+#define IA32_MC0_STATUS 0x401
#define MSR_PKG_POWER_SKU_UNIT 0x606
#define MSR_PKG_POWER_LIMIT 0x610
#define MSR_CONFIG_TDP_NOMINAL 0x648