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authorFurquan Shaikh <furquan@chromium.org>2017-08-04 15:58:26 -0700
committerFurquan Shaikh <furquan@google.com>2017-08-10 16:24:57 +0000
commit3406dd64c328bf0f2f1902d42b239f84c136e4f0 (patch)
tree3a041bafb43a260432cb0c9e2f769e5b177ad9fe
parent836f94c6126b8a9529321c6af71babdae3202592 (diff)
downloadcoreboot-3406dd64c328bf0f2f1902d42b239f84c136e4f0.tar.xz
soc/intel/common/uart: Refactor uart_common_init
1. Create a new function uart_lpss_init which takes the UART LPSS controller out of reset and initializes and enables clock. 2. Instead of passing in m/n clock divider values as parameters to uart_common_init, introduce Kconfig variables so that uart_lpss_init can use the values directly without having to query the SoC. BUG=b:64030366 TEST=Verified that UART still works on APL and KBL boards. Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/apollolake/Kconfig10
-rw-r--r--src/soc/intel/apollolake/include/soc/uart.h7
-rw-r--r--src/soc/intel/apollolake/uart_early.c2
-rw-r--r--src/soc/intel/common/block/include/intelblocks/uart.h8
-rw-r--r--src/soc/intel/common/block/uart/Kconfig12
-rw-r--r--src/soc/intel/common/block/uart/uart.c18
-rw-r--r--src/soc/intel/skylake/Kconfig9
-rw-r--r--src/soc/intel/skylake/bootblock/uart.c6
8 files changed, 51 insertions, 21 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index cc516f32ad..1323f573d1 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -351,4 +351,14 @@ config APL_SKIP_SET_POWER_LIMITS
Limits (RAPL) algorithm for a constant power management.
Set this config option to skip the RAPL configuration.
+# M and N divisor values for clock frequency configuration.
+# These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)
+config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
+ hex
+ default 0x25a
+
+config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
+ hex
+ default 0x7fff
+
endif
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
index b2b1bb8623..bf8b9d74e3 100644
--- a/src/soc/intel/apollolake/include/soc/uart.h
+++ b/src/soc/intel/apollolake/include/soc/uart.h
@@ -18,13 +18,6 @@
#ifndef _SOC_APOLLOLAKE_UART_H_
#define _SOC_APOLLOLAKE_UART_H_
-/*
-* M and N divisor values for clock frequency configuration.
-* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)
-*/
-#define CLK_M_VAL 0x025a
-#define CLK_N_VAL 0x7fff
-
/* Initialize the console UART including the pads for the configured UART. */
void pch_uart_init(void);
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
index 4c143ad854..d3c1b0d0ca 100644
--- a/src/soc/intel/apollolake/uart_early.c
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -69,6 +69,6 @@ void pch_uart_init(void)
gpio_configure_pads(&uart_gpios[pad_index * 2], 2);
/* Program UART2 BAR0, command, reset and clock register */
- uart_common_init(uart, base, CLK_M_VAL, CLK_N_VAL);
+ uart_common_init(uart, base);
}
diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h
index b46edd76d7..9ec5004e08 100644
--- a/src/soc/intel/common/block/include/intelblocks/uart.h
+++ b/src/soc/intel/common/block/include/intelblocks/uart.h
@@ -19,8 +19,12 @@
#include <arch/io.h>
#include <device/device.h>
-void uart_common_init(device_t dev, uintptr_t baseaddr,
- uint32_t clk_m_val, uint32_t clk_n_val);
+/*
+ * Common routine to initialize UART controller PCI config space, take it out of
+ * reset and configure M/N dividers.
+ */
+void uart_common_init(device_t dev, uintptr_t baseaddr);
+
void pch_uart_read_resources(struct device *dev);
diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig
index 103659f4c4..f4a0e4e4b9 100644
--- a/src/soc/intel/common/block/uart/Kconfig
+++ b/src/soc/intel/common/block/uart/Kconfig
@@ -3,3 +3,15 @@ config SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_LPSS
help
Intel Processor common UART support
+
+config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL
+ depends on SOC_INTEL_COMMON_BLOCK_UART
+ hex
+ help
+ Clock m-divisor value for m/n divider
+
+config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL
+ depends on SOC_INTEL_COMMON_BLOCK_UART
+ hex
+ help
+ Clock m-divisor value for m/n divider
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index e8f1bc8094..be30464b13 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -19,8 +19,17 @@
#include <intelblocks/lpss.h>
#include <intelblocks/uart.h>
-void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val,
- uint32_t clk_n_val)
+static void uart_lpss_init(uintptr_t baseaddr)
+{
+ /* Take UART out of reset */
+ lpss_reset_release(baseaddr);
+
+ /* Set M and N divisor inputs and enable clock */
+ lpss_clk_update(baseaddr, CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL,
+ CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL);
+}
+
+void uart_common_init(device_t dev, uintptr_t baseaddr)
{
/* Set UART base address */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr);
@@ -29,11 +38,8 @@ void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val,
pci_write_config32(dev, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- /* Take UART out of reset */
- lpss_reset_release(baseaddr);
+ uart_lpss_init(baseaddr);
- /* Set M and N divisor inputs and enable clock */
- lpss_clk_update(baseaddr, clk_m_val, clk_n_val);
}
#if ENV_RAMSTAGE
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 32c2654c4d..f0402a9e2b 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -317,4 +317,13 @@ config CPU_BCLK_MHZ
int
default 100
+# Clock divider parameters for 115200 baud rate
+config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
+ hex
+ default 0x30
+
+config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
+ hex
+ default 0xc35
+
endif
diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c
index 26b81c0589..b7ab241f77 100644
--- a/src/soc/intel/skylake/bootblock/uart.c
+++ b/src/soc/intel/skylake/bootblock/uart.c
@@ -31,10 +31,6 @@
#define PCR_SIO_PCH_LEGACY_UART1 (1 << 1)
#define PCR_SIO_PCH_LEGACY_UART2 (1 << 2)
-/* Clock divider parameters for 115200 baud rate */
-#define CLK_M_VAL 0x30
-#define CLK_N_VAL 0xc35
-
/* UART2 pad configuration. Support RXD and TXD for now. */
static const struct pad_config uart2_pads[] = {
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
@@ -45,7 +41,7 @@ void pch_uart_init(void)
{
uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
- uart_common_init(PCH_DEV_UART2, base, CLK_M_VAL, CLK_N_VAL);
+ uart_common_init(PCH_DEV_UART2, base);
/* Put UART2 in byte access mode for 16550 compatibility */
if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))