diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-08-28 17:21:07 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-08 11:31:13 +0000 |
| commit | 3745c65c832ab0abb557cf68e92a6ad2c09f0faf (patch) | |
| tree | 4268f2ab09a346f76b1427fd8071f66979437f98 | |
| parent | 15c220dc3918755b72ac7eb1e128fc65c6b64cf7 (diff) | |
| download | coreboot-3745c65c832ab0abb557cf68e92a6ad2c09f0faf.tar.xz | |
skylake: Apply USB2 and USB3 port enable/disable settings
The USB port enable/disable settings were never getting applied to
the UPD configuration and so were not getting used by FSP.
BUG=chrome-os-partner:44662
BRANCH=none
TEST=build and boot on glados
Change-Id: I13d4eb901215308de4b59083339832d29ce0049f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fd83caa8087cc349fa933eafac98c2563f501a4
Original-Change-Id: Ia5fa051782eeb837756a14aecb4aa626d25b2bdb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296034
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11547
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 8bd62b4d13..2c498838b5 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -26,6 +26,7 @@ #include <fsp_util.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include <string.h> static void pci_domain_set_resources(device_t dev) { @@ -69,18 +70,15 @@ struct chip_operations soc_intel_skylake_ops = { /* UPD parameters to be initialized before SiliconInit */ void soc_silicon_init_params(SILICON_INIT_UPD *params) { - const struct device *dev; - const struct soc_intel_skylake_config *config; - int i; + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *config = dev->chip_info; - /* Set the parameters for SiliconInit */ - dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); - if (!dev || !dev->chip_info) - return; - config = dev->chip_info; - - for (i = 0; i < PchSerialIoIndexMax; i++) - params->SerialIoDevMode[i] = config->SerialIoDevMode[i]; + memcpy(params->SerialIoDevMode, config->SerialIoDevMode, + sizeof(params->SerialIoDevMode)); + memcpy(params->PortUsb20Enable, config->PortUsb20Enable, + sizeof(params->PortUsb20Enable)); + memcpy(params->PortUsb30Enable, config->PortUsb30Enable, + sizeof(params->PortUsb30Enable)); params->SataSalpSupport = config->SataSalpSupport; params->SataPortsEnable[0] = config->SataPortsEnable[0]; |