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authorKane Chen <kane.chen@intel.com>2014-07-17 11:31:57 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-01-16 20:50:40 +0100
commit374f27bc02a9c1a2188c2c323f9773e1d429ee61 (patch)
tree9d779fb74832391761d8f16979bcedb6729a9736
parente3815442925619af88617ab572dff622a42810d1 (diff)
downloadcoreboot-374f27bc02a9c1a2188c2c323f9773e1d429ee61.tar.xz
baytrail: there is a chance that USBPHY_COMPBG is set to 0
Due to some projects don't have the correct settings in devicetree.cb so put this change in case those projects without are setting in devicetree.cb BUG=chrome-os-partner:30690 BRANCH=none TEST=emerge-rambi coreboot without problem checked the USBPHY_COMPBG is configured properly even there is no setting in devicetree Original-Change-Id: Iaf8155497c41f10c81d1faa7bb0e3452a7cedcc6 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209051 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 713f809952a2d8da434d619d48cb7ddce1991925) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I86f9b77e703d2b844fa636678499c47ffaffeede Reviewed-on: http://review.coreboot.org/8218 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/soc/intel/baytrail/ehci.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c
index bfdb61aa1a..74577af4a8 100644
--- a/src/soc/intel/baytrail/ehci.c
+++ b/src/soc/intel/baytrail/ehci.c
@@ -94,10 +94,12 @@ static const struct reg_script ehci_hc_reset[] = {
static void usb2_phy_init(device_t dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
+ u32 usb2_comp_bg = (config->usb2_comp_bg == 0 ?
+ 0x4700 : config->usb2_comp_bg);
struct reg_script usb2_phy_script[] = {
/* USB3PHYInit() */
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG,
- config->usb2_comp_bg),
+ usb2_comp_bg),
/* Per port phy settings, set in devicetree.cb */
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0,
config->usb2_per_port_lane0),