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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-21 16:19:32 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-22 18:37:57 +0000 |
| commit | 382e2167ccf29622fde208e3443e244ddec42ea6 (patch) | |
| tree | b02537278e9b8d4239f4143e12597cb1b8fe85f2 | |
| parent | 853c1afac21f3cfd19f487e95ba2b53cbd80e241 (diff) | |
| download | coreboot-382e2167ccf29622fde208e3443e244ddec42ea6.tar.xz | |
device/pci: Replace add with bitwise-or
Change-Id: I9fbefac3bef7425d6f5ea1bcc01eb21485315c36
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/device/cardbus_device.c | 2 | ||||
| -rw-r--r-- | src/device/pci_device.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pci.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/pci.c | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index a4407463c7..4b24c54df7 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -159,7 +159,7 @@ void cardbus_enable_resources(struct device *dev) PCI_BRIDGE_CTL_MASTER_ABORT | PCI_BRIDGE_CTL_BUS_RESET)); /* Error check */ - ctrl |= (PCI_CB_BRIDGE_CTL_PARITY + PCI_CB_BRIDGE_CTL_SERR); + ctrl |= (PCI_CB_BRIDGE_CTL_PARITY | PCI_CB_BRIDGE_CTL_SERR); printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7ecb652d34..c043dd6591 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -626,7 +626,7 @@ void pci_bus_enable_resources(struct device *dev) dev->command |= PCI_COMMAND_IO; ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); ctrl |= dev->link_list->bridge_ctrl; - ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */ + ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* Error check. */ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 2186287df2..6391de409c 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -77,7 +77,7 @@ static void ich_pci_bus_enable_resources(struct device *dev) dev->command |= PCI_COMMAND_IO; ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); ctrl |= dev->link_list->bridge_ctrl; - ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ + ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* error check */ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 22c516581f..1d1f902727 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -76,7 +76,7 @@ static void ich_pci_bus_enable_resources(struct device *dev) dev->command |= PCI_COMMAND_IO; ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); ctrl |= dev->link_list->bridge_ctrl; - ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ + ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* error check */ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); |