diff options
| author | Gabe Black <gabeblack@chromium.org> | 2013-05-29 16:42:20 +0200 |
|---|---|---|
| committer | David Hendricks <dhendrix@chromium.org> | 2013-06-03 03:10:17 +0200 |
| commit | 3aa58162e1be25ad77800879e73a087ddbdc660c (patch) | |
| tree | 284f5d515de93b2fa21d7771885e3ec1544e5eb5 | |
| parent | 29a435597345e1e05a449f2e864c8e3746538c45 (diff) | |
| download | coreboot-3aa58162e1be25ad77800879e73a087ddbdc660c.tar.xz | |
am335x: Clean up/fix some settings in the am335x Kconfig.
Some settings in the am335x Kconfig weren't actually used for anything, some
where place holders, and some where left over from another CPU. The memory
addresses are in the internal RAM in the SOC as described in the reference
manual. The stack is put where the internal ROM had its stack, and the
bootblock is put at the bottom of that region as the manual suggests. The
ROM stage offset is set to 10K which is a bit bigger than the ~7.5K the
bootblock currently takes up.
Change-Id: I1a117d789a791d7e3db1118823f8216b3361433c
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3327
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
| -rw-r--r-- | src/cpu/ti/am335x/Kconfig | 39 |
1 files changed, 4 insertions, 35 deletions
diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index c4ef8f1703..472fbe7b34 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -6,25 +6,9 @@ config BOOTBLOCK_CPU_INIT bootblock must load microcode or copy data from ROM before searching for the bootblock. -# Example SRAM/iRAM map for Exynos5250 platform: -# -# 0x0202_3400: bootblock, assume up to 32KB in size -# 0x0203_0000: romstage, assume up to 128KB in size. -# 0x0207_8000: stack pointer - -# FIXME: find out where romboot places ml0/coreboot config BOOTBLOCK_BASE hex - default 0xdeadbeef - -#config ROMSTAGE_BASE -# hex -# default 0x02030000 -# -# FIXME: this is bullshit. -config ROMSTAGE_SIZE - hex - default 0xa000 + default 0x402f0400 # Stack may reside in either IRAM or DRAM. We will define it to live # at the top of IRAM for now. @@ -33,11 +17,11 @@ config ROMSTAGE_SIZE # consecutive memory locations ending just below SP config STACK_TOP hex - default 0x02078000 + default 0x4030ce00 config STACK_BOTTOM hex - default 0x02077000 + default 0x4030be00 config STACK_SIZE hex @@ -46,7 +30,7 @@ config STACK_SIZE config CBFS_ROM_OFFSET # Calculated by BL1 + max bootblock size. hex "offset of CBFS data in ROM" - default 0x0A000 + default 0x2800 ## TODO Change this to some better address not overlapping bootblock when ## cbfstool supports creating header in arbitrary location. @@ -54,21 +38,6 @@ config CBFS_HEADER_ROM_OFFSET hex "offset of master CBFS header in ROM" default 0x40 -## TODO We may probably move this to board-specific implementation files instead -## of KConfig values. -#config CBFS_CACHE_ADDRESS -# hex "memory address to put CBFS cache data" -# default 0x02060000 -# -#config CBFS_CACHE_SIZE -# hex "size of CBFS cache data" -# default 0x000017000 - -# FIXME: other magic numbers that should probably go away -config XIP_ROM_SIZE - hex - default ROMSTAGE_SIZE - config SYS_SDRAM_BASE hex default 0x40000000 |