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authorKane Chen <kane.chen@intel.com>2017-05-31 18:36:45 +0800
committerAaron Durbin <adurbin@chromium.org>2017-06-03 07:18:18 +0200
commit4db78e39dafa78a65ca9794e9344ce99f699740a (patch)
tree9ae17b89e876f34362e7b65af1ba78c41337cd78
parentf4835a85c0e851d13bcfed53a23f495caeefe8e2 (diff)
downloadcoreboot-4db78e39dafa78a65ca9794e9344ce99f699740a.tar.xz
soc/intel/skylake: Add macro for setting GPIO interrupt trigger mode.
Currently, there is no macro to set GPIO interrupt trigger mode. The purpose is to make coreboot set same trigger mode as GpioInt BUG=b:62067569 TEST=checked unused interrupt on SD_CD does not happen after s3 resume Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/19992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/soc/intel/skylake/include/soc/gpio.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index ae534cd9ce..4f809cf480 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -140,6 +140,12 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num);
_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\
PAD_FIELD(HOSTSW, GPIO))
+/* General purpose input passed through to GPIO interrupt */
+#define PAD_CFG_GPI_INT(pad_, term_, rst_, trig_) \
+ _PAD_CFG_ATTRS(pad_, term_, \
+ _DW0_VALS(rst_, RAW, NO, trig_, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\
+ PAD_FIELD(HOSTSW, GPIO))
+
/* General purpose input passed through to IOxAPIC. Assume APIC logic can
* handle polarity/edge/level constraints. */
#define PAD_CFG_GPI_APIC(pad_, term_, rst_) \