diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-23 18:40:15 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-07 10:31:52 +0000 |
| commit | 5493b4543d80e6cabe4ce60341f0a02f1711da66 (patch) | |
| tree | faa4e863115dc9553db7179a82ae1d8babb7f05b | |
| parent | a3a2ffbe57f30df4575855d923abc56e5245fd59 (diff) | |
| download | coreboot-5493b4543d80e6cabe4ce60341f0a02f1711da66.tar.xz | |
sb/intel/bd82x6x: Fix typo in GPIO Level
Change-Id: I5e24120ca788ace8b61f8a7aee177c7247d30de2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/pch.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index d3aa7a4406..72e284d08f 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -87,7 +87,7 @@ Scope(\) GIO2, 8, GIO3, 8, Offset(0x0c), // GPIO Level - GL00, 1, + GP00, 1, GP01, 1, GP02, 1, GP03, 1, |