diff options
author | Martin Roth <martinroth@google.com> | 2016-01-06 16:24:49 -0700 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-01-12 22:24:09 +0100 |
commit | 5559e8935e71416946efc46c0fb3fec470aa45a4 (patch) | |
tree | 6af5bf3c4b819fb0954425cca83047056863f054 | |
parent | 8e6b0a2ae25176028615aa45c0b8e341ff622a61 (diff) | |
download | coreboot-5559e8935e71416946efc46c0fb3fec470aa45a4.tar.xz |
intel/skylake: Remove check for Microcode loaded by ME
This method of reporting has been removed from the current Skylake
ME binaries so is no longer needed.
Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12854
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
-rw-r--r-- | src/soc/intel/skylake/bootblock/cpu.c | 23 |
1 files changed, 1 insertions, 22 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index bc9d63826d..6fc4d92662 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -171,32 +171,11 @@ static void check_for_clean_reset(void) soft_reset(); } -static void patch_microcode(void) -{ - const struct microcode *patch; - u32 current_rev; - msr_t msr; - - patch = intel_microcode_find(); - - current_rev = read_microcode_rev(); - - /* If PRMRR/SGX is supported the FIT microcode load step will set - * msr 0x08b with the Patch revision id one less than the id in the - * microcode binary. The PRMRR support is indicated in the MSR - * MTRRCAP[12]. Check for this feature and avoid reloading the - * same microcode during early cpu initialization. - */ - msr = rdmsr(MTRR_CAP_MSR); - if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1)) - intel_update_microcode_from_cbfs(); -} - static void bootblock_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); check_for_clean_reset(); enable_rom_caching(); - patch_microcode(); + intel_update_microcode_from_cbfs(); } |