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authorVadim Bendebury <vbendeb@chromium.org>2016-04-22 16:06:26 -0700
committerPatrick Georgi <pgeorgi@google.com>2016-05-09 08:50:16 +0200
commit591298a575d6815346c312bb5254f77abef56fb8 (patch)
treea4efba3c6441c50d407657717ba442de6800f8ce
parent8e8a00cabfacb3c0c4f16465c94386bfdb615a47 (diff)
downloadcoreboot-591298a575d6815346c312bb5254f77abef56fb8.tar.xz
google/gru: enable pp1500 and pp3000 rails as soon as possible
The idea is that they stay low unless we know that we booted from SPI flash. As this code runs in SPI flash - it is ok to turn these rails on as soon as possible, and pp3000 rail it is essential for UART to work. Kevin rev1 and Gru designs are going to be using these pins to control these rails. Kevin rev1 had those GPIO pins routed to two chip enable signals, it is save to assert them high. BRANCH=none BUG=chrome-os-partner:51537 TEST=kevin rev0 still boots (which does not prove much) TEST=run coreboot on kevin rev1 to kernel Change-Id: I5f3eb4cf5d6f04a0253574dd8b5c039eab0bae1a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 987042246672e9391087dbd5060785a379dde131 Original-Change-Id: I31bb03334ad9e3aa57db726fb43dec85014a3f05 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/341543 Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/14729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/mainboard/google/gru/bootblock.c8
-rw-r--r--src/soc/rockchip/rk3399/Makefile.inc2
2 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index 74e02b273f..1166d8a842 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -17,6 +17,7 @@
#include <arch/io.h>
#include <bootblock_common.h>
#include <soc/grf.h>
+#include <gpio.h>
#include <soc/spi.h>
#include <console/console.h>
@@ -35,6 +36,13 @@ void bootblock_mainboard_early_init(void)
*/
write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 0));
+ /*
+ * Let's enable these power rails here, we are already running the SPI
+ * Flash based code.
+ */
+ gpio_output(GPIO(0, B, 2), 1); /* PP1500_EN */
+ gpio_output(GPIO(0, B, 4), 1); /* PP3000_EN */
+
if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
_Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE,
"CONSOLE_SERIAL_UART should be UART2");
diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc
index 387d3770d8..4d5091df76 100644
--- a/src/soc/rockchip/rk3399/Makefile.inc
+++ b/src/soc/rockchip/rk3399/Makefile.inc
@@ -21,8 +21,10 @@ bootblock-y += ../common/spi.c
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c
endif
+bootblock-y += ../common/gpio.c
bootblock-y += bootblock.c
bootblock-y += clock.c
+bootblock-y += gpio.c
bootblock-y += mmu_operations.c
bootblock-y += timer.c