diff options
| author | Nico Huber <nico.huber@secunet.com> | 2015-11-04 15:46:00 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2015-11-05 16:09:42 +0100 |
| commit | 593e7de5a777db0310da7221f81982b6b3ed4929 (patch) | |
| tree | f8b848910eba76c2b9b85546cd79086f74ebbe29 | |
| parent | 855fc1fcdbf1e40931d31f25ca7091a7b0aeace5 (diff) | |
| download | coreboot-593e7de5a777db0310da7221f81982b6b3ed4929.tar.xz | |
nb/intel/sandybridge: Limit GFX workaround to Sandy Bridge
The touched workaround for Sandy Bridge reserves two memory regions that
could cause graphics corruption if mapped by the integrated graphics
device. To the best of our knowledge, the workaround is not needed for
Ivy Bridge revisions.
Tested on kontron/ktqm77 (Ivy Bridge): Booted Linux and checked the
memory regions are not reserved. Couldn't test on Sandy Bridge, due to
lack of hardware.
Change-Id: I4273d1d804b490cf93c23426782eb1ffaf29f7d4
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12326
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Tested-by: build bot (Jenkins)
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 08a0c9d709..bfc5de85a5 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -124,9 +124,11 @@ static void add_fixed_resources(struct device *dev, int index) CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); #endif - /* Required for SandyBridge sighting 3715511 */ - bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); - bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + /* Required for SandyBridge sighting 3715511 */ + bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); + bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); + } /* Reserve IOMMU BARs */ const u32 capid0_a = pci_read_config32(dev, 0xe4); |