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authorIvy Jian <ivy_jian@compal.corp-partner.google.com>2019-09-10 10:40:42 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-09-12 13:17:04 +0000
commit59674c984e637e4edad08e257bbfcae55a2d07c9 (patch)
tree36f1c7ca5f4c6a53b9f717bba6220db145407207
parent8cced29eed33285e0a086231c567f4633372f004 (diff)
downloadcoreboot-59674c984e637e4edad08e257bbfcae55a2d07c9.tar.xz
mb/google/drallion: Update memory map
This will increase ME region size and reduce the BIOS region size. BUG=b:140665483 TEST='compile successfully' Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35304 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/drallion/chromeos.fmd22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd
index 78b12bd8bd..8bab919c6d 100644
--- a/src/mainboard/google/drallion/chromeos.fmd
+++ b/src/mainboard/google/drallion/chromeos.fmd
@@ -1,26 +1,26 @@
FLASH@0xfe000000 0x2000000 {
- SI_ALL@0x0 0x402000 {
+ SI_ALL@0x0 0x438000 {
SI_DESC@0x0 0x1000
SI_EC@0x1000 0x100000
- SI_ME@0x101000 0x2fd000
- SI_PDR(PRESERVE)@0x3fe000 0x4000
+ SI_ME@0x101000 0x333000
+ SI_PDR(PRESERVE)@0x434000 0x4000
}
- SI_BIOS@0x402000 0x1bfe000 {
- RW_DIAG@0x0 0x12ce000 {
- RW_LEGACY(CBFS)@0x0 0x12be000
- DIAG_NVRAM@0x12be000 0x10000
+ SI_BIOS@0x438000 0x1bc8000 {
+ RW_DIAG@0x0 0x1298000 {
+ RW_LEGACY(CBFS)@0x0 0x1288000
+ DIAG_NVRAM@0x1288000 0x10000
}
- RW_SECTION_A@0x12ce000 0x280000 {
+ RW_SECTION_A@0x1298000 0x280000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x26ffc0
RW_FWID_A@0x27ffc0 0x40
}
- RW_SECTION_B@0x154e000 0x280000 {
+ RW_SECTION_B@0x1518000 0x280000 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x26ffc0
RW_FWID_B@0x27ffc0 0x40
}
- RW_MISC@0x17ce000 0x30000 {
+ RW_MISC@0x1798000 0x30000 {
UNIFIED_MRC_CACHE@0x0 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
@@ -33,7 +33,7 @@ FLASH@0xfe000000 0x2000000 {
RW_VPD(PRESERVE)@0x28000 0x2000
RW_NVRAM(PRESERVE)@0x2a000 0x6000
}
- WP_RO@0x17fe000 0x400000 {
+ WP_RO@0x17c8000 0x400000 {
RO_VPD(PRESERVE)@0x0 0x4000
RO_UNUSED@0x4000 0xc000
RO_SECTION@0x10000 0x3f0000 {