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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-06-19 23:05:00 +0300
committerRonald G. Minnich <rminnich@gmail.com>2013-06-25 08:03:52 +0200
commit59fb82aab1554889d4e51d988eb8927c7d31babd (patch)
treec5ea9a01d60614e1d333d0361ab5cdbe8055872f
parent66a68a2af8b9c65d3d86a49459ed8217347d2cb1 (diff)
downloadcoreboot-59fb82aab1554889d4e51d988eb8927c7d31babd.tar.xz
intel/sch: Use MMCONF_BASE_ADDRESS
For iwave/iWRainbowG6 using intel/sch, MMCONF_BASE_ADDRESS was unused and different from hardware setting. Change that to match hardware programming. Change-Id: I3324b7ea0e6f092206d4b6b791476d538e826657 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3507 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
-rw-r--r--src/mainboard/iwave/iWRainbowG6/Kconfig2
-rw-r--r--src/northbridge/intel/sch/sch.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig
index 7e05aaea80..e908fcf095 100644
--- a/src/mainboard/iwave/iWRainbowG6/Kconfig
+++ b/src/mainboard/iwave/iWRainbowG6/Kconfig
@@ -26,7 +26,7 @@ config MAINBOARD_PART_NUMBER
config MMCONF_BASE_ADDRESS
hex
- default 0xf0000000
+ default 0xe0000000
config IRQ_SLOT_COUNT
int
diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h
index 4f49beb041..5700842e90 100644
--- a/src/northbridge/intel/sch/sch.h
+++ b/src/northbridge/intel/sch/sch.h
@@ -38,7 +38,7 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);
#define DEFAULT_RCBABASE 0xfed1c000
-#define DEFAULT_PCIEXBAR 0xe0000000 /* 4 KB per PCIe device */
+#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
/* IGD */
#define GGC 0x52