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authorPatrick Georgi <pgeorgi@google.com>2015-07-31 17:27:23 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-08-09 21:57:57 +0200
commit61234909f8ac02f3a0a5af2826a9b5b702a2bb9e (patch)
treeb0534497bf057c32d6fa583dfd8f033024d158ca
parent6f0e8bdc169e152a8065694c5ef69f0a654d9f31 (diff)
downloadcoreboot-61234909f8ac02f3a0a5af2826a9b5b702a2bb9e.tar.xz
imgtech/pistacho: Add vboot2 memory region
Change-Id: I375397d4a1db6fef6b40421590f315c0f7eb0948 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11100 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/soc/imgtec/pistachio/include/soc/memlayout.ld4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index b36d47e9b6..366b20ac91 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,6 +18,7 @@
*/
#include <memlayout.h>
+#include <vendorcode/google/chromeos/memlayout.h>
#include <arch/header.ld>
@@ -39,7 +40,8 @@ SECTIONS
*/
SRAM_START(0x1a000000)
ROMSTAGE(0x1a005000, 40K)
- PRERAM_CBFS_CACHE(0x1a00f000, 68K)
+ VBOOT2_WORK(0x1a00f000, 12K)
+ PRERAM_CBFS_CACHE(0x1a012000, 56K)
SRAM_END(0x1a020000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping.