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authorMatt DeVillier <matt.devillier@gmail.com>2018-01-21 18:28:38 -0600
committerPatrick Georgi <pgeorgi@google.com>2018-03-08 17:49:05 +0000
commit62bef5a6bebbb01f00fd3f11488db749b005087e (patch)
treef1f5bc7d8dd7b2ac2ceeb78d20a255f1ddc78a5f
parentcbedd8fd2a09da5ca98b536cfa6a089555e4520d (diff)
downloadcoreboot-62bef5a6bebbb01f00fd3f11488db749b005087e.tar.xz
soc/intel/braswell: add ACPI for eMMC/SD devices in PCI mode
Allows eMMC in PCI mode to be seen/used by Windows. Test: boot Windows installer on google/edgar, observe internal eMMC storage available for installation when eMMC in PCI (vs ACPI) mode. Change-Id: I4272c198e5e675f451a1f4de5d46e3cd96371446 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/braswell/acpi/scc.asl38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/acpi/scc.asl b/src/soc/intel/braswell/acpi/scc.asl
index 95f224435d..128edc55d6 100644
--- a/src/soc/intel/braswell/acpi/scc.asl
+++ b/src/soc/intel/braswell/acpi/scc.asl
@@ -77,6 +77,44 @@ Device (EMMC)
}
}
+Device (PEMC)
+{
+ Name (_ADR, 0x00100000) // _ADR: Address
+
+ OperationRegion (SDIO, PCI_Config, 0x84, 0x04)
+ Field (SDIO, WordAcc, NoLock, Preserve)
+ {
+ Offset (0x01),
+ PMEE, 1,
+ , 6,
+ PMES, 1
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ If (LEqual (\C0EN, 1)) {
+ Return (0x0)
+ }
+ Else
+ {
+ Return (0xF)
+ }
+ }
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ }
+
+ Device (CARD)
+ {
+ Name (_ADR, 0x08)
+ Method (_RMV, 0, NotSerialized)
+ {
+ Return (Zero)
+ }
+ }
+}
+
Device (SDIO)
{
Name (_HID, "INT33BB")