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authorArthur Heymans <arthur@aheymans.xyz>2018-01-25 21:38:25 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-23 14:45:34 +0000
commit6336d4c48d2f85629ff668da36711ea794f70ab5 (patch)
tree1cafe0dde00967c76897312d80fca723bf0a2f79
parentea415b335f57bde8e744e0f40845cc6fdd671c71 (diff)
downloadcoreboot-6336d4c48d2f85629ff668da36711ea794f70ab5.tar.xz
nb/intel/gm45: Use parallel MP init
This places the parallel mp ops up in the model_1067x dir and is included from other Intel core2 CPU dirs that can use the same code. Tested on Thinkpad X200 on which boot time is reduced by ~35ms. Change-Id: Iac416f671407246ee223075eee1aff511e612889 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/23434 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/cpu/intel/model_1067x/Makefile.inc1
-rw-r--r--src/cpu/intel/model_1067x/model_1067x_init.c14
-rw-r--r--src/cpu/intel/model_1067x/mp_init.c85
-rw-r--r--src/cpu/intel/model_6fx/Makefile.inc1
-rw-r--r--src/cpu/intel/model_6fx/model_6fx_init.c12
-rw-r--r--src/northbridge/intel/gm45/Kconfig1
-rw-r--r--src/northbridge/intel/gm45/northbridge.c22
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c3
8 files changed, 109 insertions, 30 deletions
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index 133c9cff8f..451df6ef35 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,5 @@
ramstage-y += model_1067x_init.c
+ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c
subdirs-y += ../../x86/name
subdirs-y += ../common
subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index dbb9631ad8..8f8af57037 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -21,12 +21,14 @@
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
+#include <cpu/x86/mp.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/smm/gen1/smi.h>
#include <cpu/intel/common/common.h>
#include "chip.h"
@@ -279,15 +281,18 @@ static void model_1067x_init(struct device *cpu)
x86_enable_cache();
/* Update the microcode */
- intel_update_microcode_from_cbfs();
+ if (!IS_ENABLED(CONFIG_PARALLEL_MP))
+ intel_update_microcode_from_cbfs();
/* Print processor name */
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
/* Setup MTRRs */
- x86_setup_mtrrs();
- x86_mtrr_check();
+ if (!IS_ENABLED(CONFIG_PARALLEL_MP)) {
+ x86_setup_mtrrs();
+ x86_mtrr_check();
+ }
/* Enable the local CPU APICs */
setup_lapic();
@@ -315,7 +320,8 @@ static void model_1067x_init(struct device *cpu)
configure_pic_thermal_sensors(tm2, quad);
/* Start up my CPU siblings */
- intel_sibling_init(cpu);
+ if (!IS_ENABLED(CONFIG_PARALLEL_MP))
+ intel_sibling_init(cpu);
}
static struct device_operations cpu_dev_ops = {
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
new file mode 100644
index 0000000000..52e9d3f010
--- /dev/null
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/mp.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/common/common.h>
+
+/* Parallel MP initialization support. */
+static const void *microcode_patch;
+
+static void pre_mp_init(void)
+{
+ /* Setup MTRRs based on physical address size. */
+ x86_setup_mtrrs_with_detect();
+ x86_mtrr_check();
+}
+
+static int get_cpu_count(void)
+{
+ const struct cpuid_result cpuid1 = cpuid(1);
+ const char cores = (cpuid1.ebx >> 16) & 0xf;
+
+ printk(BIOS_DEBUG, "CPU has %u cores.\n", cores);
+
+ return cores;
+}
+
+/* the SMRR enable and lock bit need to be set in IA32_FEATURE_CONTROL
+ to enable SMRR so configure IA32_FEATURE_CONTROL early on */
+static void pre_mp_smm_init(void)
+{
+ smm_initialize();
+}
+
+static void per_cpu_smm_trigger(void)
+{
+ /* Relocate the SMM handler. */
+ smm_relocate();
+
+ /* After SMM relocation a 2nd microcode load is required. */
+ intel_microcode_load_unlocked(microcode_patch);
+}
+
+static void post_mp_init(void)
+{
+ /* Now that all APs have been relocated as well as the BSP let SMIs
+ * start flowing. */
+ southbridge_smm_init();
+
+ /* Lock down the SMRAM space. */
+ smm_lock();
+}
+
+static const struct mp_ops mp_ops = {
+ .pre_mp_init = pre_mp_init,
+ .get_cpu_count = get_cpu_count,
+ .get_smm_info = smm_info,
+ .pre_mp_smm_init = pre_mp_smm_init,
+ .per_cpu_smm_trigger = per_cpu_smm_trigger,
+ .relocation_handler = smm_relocation_handler,
+ .post_mp_init = post_mp_init,
+};
+
+void bsp_init_and_start_aps(struct bus *cpu_bus)
+{
+ if (mp_init_with_smm(cpu_bus, &mp_ops))
+ printk(BIOS_ERR, "MP initialization failure.\n");
+}
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index a0824fdb18..9564bf950e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,6 +1,7 @@
ramstage-y += model_6fx_init.c
subdirs-y += ../../x86/name
subdirs-y += ../common
+ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 9d11478dee..a502826c77 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -133,15 +133,18 @@ static void model_6fx_init(struct device *cpu)
x86_enable_cache();
/* Update the microcode */
- intel_update_microcode_from_cbfs();
+ if (!IS_ENABLED(CONFIG_PARALLEL_MP))
+ intel_update_microcode_from_cbfs();
/* Print processor name */
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
/* Setup MTRRs */
- x86_setup_mtrrs();
- x86_mtrr_check();
+ if (!IS_ENABLED(CONFIG_PARALLEL_MP)) {
+ x86_setup_mtrrs();
+ x86_mtrr_check();
+ }
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
@@ -162,7 +165,8 @@ static void model_6fx_init(struct device *cpu)
configure_pic_thermal_sensors();
/* Start up my CPU siblings */
- intel_sibling_init(cpu);
+ if (!IS_ENABLED(CONFIG_PARALLEL_MP))
+ intel_sibling_init(cpu);
}
static struct device_operations cpu_dev_ops = {
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index e7b96037dd..ef6b4ef582 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -29,6 +29,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select POSTCAR_STAGE
select POSTCAR_CONSOLE
select SMM_TSEG
+ select PARALLEL_MP
config CBFS_SIZE
hex
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 7ff046e9f3..791559b518 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -230,26 +230,6 @@ void northbridge_write_smram(u8 smram)
pci_write_config8(dev, D0F0_SMRAM, smram);
}
-/*
- * Really doesn't belong here but will go away with parallel mp init,
- * so let it be here for a while...
- */
-int cpu_get_apic_id_map(int *apic_id_map)
-{
- unsigned int i;
-
- /* Logical processors (threads) per core */
- const struct cpuid_result cpuid1 = cpuid(1);
- /* Read number of cores. */
- const char cores = (cpuid1.ebx >> 16) & 0xf;
-
- /* TODO in parallel MP cpuid(1).ebx */
- for (i = 0; i < cores; i++)
- apic_id_map[i] = i;
-
- return cores;
-}
-
static struct device_operations pci_domain_ops = {
.read_resources = mch_domain_read_resources,
.set_resources = mch_domain_set_resources,
@@ -264,7 +244,7 @@ static struct device_operations pci_domain_ops = {
static void cpu_bus_init(struct device *dev)
{
- initialize_cpus(dev->link_list);
+ bsp_init_and_start_aps(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index e18f616b82..f9e11140ff 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -393,7 +393,8 @@ static void i82801ix_lock_smm(struct device *dev)
/* Don't allow evil boot loaders, kernels, or
* userspace applications to deceive us:
*/
- smm_lock();
+ if (!IS_ENABLED(CONFIG_PARALLEL_MP))
+ smm_lock();
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */