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authorAngel Pons <th3fanbus@gmail.com>2020-01-10 02:03:47 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-01-14 12:39:37 +0000
commit63ae8dec797098f65c409842d4825730fecd79d2 (patch)
tree5df67ea4cb3ff3ab34b6908ba213734fbf7a75d3
parent2883f7af94c51bc2105fc5e5447c1f61e5c357ee (diff)
downloadcoreboot-63ae8dec797098f65c409842d4825730fecd79d2.tar.xz
nb/intel/sandybridge: Drop 'or zero' instances
Change-Id: Icd0dfdf311ac141992ec6a6026ca92e54e8d2094 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c15
1 files changed, 6 insertions, 9 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 3e17328ce9..4c3660003e 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1771,8 +1771,7 @@ static void precharge(ramctr_timing *ctrl)
/* DRAM command RD */
MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105;
MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003;
- MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) =
- (slotrank << 24) | 0;
+ MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24;
MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0;
/* DRAM command RD */
@@ -1821,8 +1820,7 @@ static void precharge(ramctr_timing *ctrl)
/* DRAM command RD */
MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105;
MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003;
- MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) =
- (slotrank << 24) | 0;
+ MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24;
MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0;
/* DRAM command RD */
@@ -2562,8 +2560,7 @@ int discover_edges(ramctr_timing *ctrl)
/* DRAM command RD */
MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105;
MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003;
- MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) =
- (slotrank << 24) | 0;
+ MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24;
MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0;
/* DRAM command RD */
@@ -2617,7 +2614,7 @@ int discover_edges(ramctr_timing *ctrl)
MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105;
MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003;
MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) =
- (slotrank << 24) | 0;
+ (slotrank << 24);
MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0;
/* DRAM command RD */
@@ -3069,13 +3066,13 @@ int channel_test(ramctr_timing *ctrl)
/* DRAM command WR */
MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x0001f201;
MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x08281064;
- MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = 0x00000000 | (slotrank << 24);
+ MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24;
MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x00000242;
/* DRAM command RD */
MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x0001f105;
MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x04281064;
- MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = 0x00000000 | (slotrank << 24);
+ MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24;
MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x00000242;
/* DRAM command PRE */