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authorGwendal Grignou <gwendal@chromium.org>2018-06-28 10:06:46 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-07-02 07:25:05 +0000
commit6459e427e8d59e7db23b2d7265205cd0b5a7d593 (patch)
tree7ef9322952276687d81de1bff8af282cee8ec26b
parentbac90c00b105a182933988bf2b589675af23a2a7 (diff)
downloadcoreboot-6459e427e8d59e7db23b2d7265205cd0b5a7d593.tar.xz
nocturne: Fix casing for register definition
Use lower case for hex values. BUG=b:74363445 TEST=compile Change-Id: I24afea58b1a791fac3c87ad397a696f7f6e0d127 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/27264 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/poppy/variants/nocturne/devicetree.cb28
1 files changed, 14 insertions, 14 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 91c0b44990..09b7ef930a 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -305,15 +305,15 @@ chip soc/intel/skylake
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)"
register "speed" = "I2C_SPEED_FAST_PLUS"
register "uid" = "0"
- register "reg_prox_ctrl0" = "0x1A"
+ register "reg_prox_ctrl0" = "0x1a"
register "reg_prox_ctrl1" = "0x00"
register "reg_prox_ctrl2" = "0x84"
- register "reg_prox_ctrl3" = "0x0E"
+ register "reg_prox_ctrl3" = "0x0e"
register "reg_prox_ctrl4" = "0x07"
- register "reg_prox_ctrl5" = "0xC6"
+ register "reg_prox_ctrl5" = "0xc6"
register "reg_prox_ctrl6" = "0x20"
- register "reg_prox_ctrl7" = "0x0D"
- register "reg_prox_ctrl8" = "0x8D"
+ register "reg_prox_ctrl7" = "0x0d"
+ register "reg_prox_ctrl8" = "0x8d"
register "reg_prox_ctrl9" = "0x43"
register "reg_prox_ctrl10" = "0x11"
register "reg_prox_ctrl11" = "0x00"
@@ -326,8 +326,8 @@ chip soc/intel/skylake
register "reg_prox_ctrl18" = "0x00"
register "reg_prox_ctrl19" = "0x00"
register "reg_sar_ctrl0" = "0x50"
- register "reg_sar_ctrl1" = "0x8A"
- register "reg_sar_ctrl2" = "0x3C"
+ register "reg_sar_ctrl1" = "0x8a"
+ register "reg_sar_ctrl2" = "0x3c"
device i2c 28 on end
end
end # I2C #1
@@ -346,15 +346,15 @@ chip soc/intel/skylake
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D10_IRQ)"
register "speed" = "I2C_SPEED_FAST_PLUS"
register "uid" = "1"
- register "reg_prox_ctrl0" = "0x1A"
+ register "reg_prox_ctrl0" = "0x1a"
register "reg_prox_ctrl1" = "0x00"
register "reg_prox_ctrl2" = "0x84"
- register "reg_prox_ctrl3" = "0x0E"
+ register "reg_prox_ctrl3" = "0x0e"
register "reg_prox_ctrl4" = "0x07"
- register "reg_prox_ctrl5" = "0xC6"
+ register "reg_prox_ctrl5" = "0xc6"
register "reg_prox_ctrl6" = "0x20"
- register "reg_prox_ctrl7" = "0x0D"
- register "reg_prox_ctrl8" = "0x8D"
+ register "reg_prox_ctrl7" = "0x0d"
+ register "reg_prox_ctrl8" = "0x8d"
register "reg_prox_ctrl9" = "0x43"
register "reg_prox_ctrl10" = "0x11"
register "reg_prox_ctrl11" = "0x00"
@@ -367,8 +367,8 @@ chip soc/intel/skylake
register "reg_prox_ctrl18" = "0x00"
register "reg_prox_ctrl19" = "0x00"
register "reg_sar_ctrl0" = "0x50"
- register "reg_sar_ctrl1" = "0x8A"
- register "reg_sar_ctrl2" = "0x3C"
+ register "reg_sar_ctrl1" = "0x8a"
+ register "reg_sar_ctrl2" = "0x3c"
device i2c 28 on end
end
end # I2C #5