soc/intel/icelake: Move power_state functions to pmutil.c

This patch ports CB:31787 and CB:31908 changes from CNL to ICL.

This change moves soc_fill_power_state and soc_prev_sleep_state to
pmutil.c. It allows the functions to be used across romstage and smm.

Also fix GEN_PMCON bit checks as below:
ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A
and so this change updates the check for these bits to use GEN_PMCON_A
instead of GEN_PMCON_B.

Change-Id: Ib7ab95b7bbcc97a076d27a11db2105f7b976b521
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32506
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 64 insertions, 87 deletions

diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c
index e1b1665368..1c47783555 100644
--- a/src/soc/intel/icelake/pmutil.c
+++ b/src/soc/intel/icelake/pmutil.c
@@ -210,3 +210,67 @@ int vbnv_cmos_failed(void)
 {
 	return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
 }
+
+static inline int deep_s3_enabled(void)
+{
+	uint32_t deep_s3_pol;
+
+	deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
+	return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
+}
+
+/* Return 0, 3, or 5 to indicate the previous sleep state. */
+int soc_prev_sleep_state(const struct chipset_power_state *ps,
+	int prev_sleep_state)
+{
+
+	/*
+	 * Check for any power failure to determine if this a wake from
+	* S5 because the PCH does not set the WAK_STS bit when waking
+	* from a true G3 state.
+	*/
+	if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))
+		prev_sleep_state = ACPI_S5;
+
+	/*
+	 * If waking from S3 determine if deep S3 is enabled. If not,
+	 * need to check both deep sleep well and normal suspend well.
+	 * Otherwise just check deep sleep well.
+	 */
+	if (prev_sleep_state == ACPI_S3) {
+		/* PWR_FLR represents deep sleep power well loss. */
+		uint32_t mask = PWR_FLR;
+
+		/* If deep s3 isn't enabled check the suspend well too. */
+		if (!deep_s3_enabled())
+			mask |= SUS_PWR_FLR;
+
+		if (ps->gen_pmcon_a & mask)
+			prev_sleep_state = ACPI_S5;
+	}
+
+	return prev_sleep_state;
+}
+
+void soc_fill_power_state(struct chipset_power_state *ps)
+{
+	uint8_t *pmc;
+
+	ps->tco1_sts = tco_read_reg(TCO1_STS);
+	ps->tco2_sts = tco_read_reg(TCO2_STS);
+
+	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n",
+	ps->tco1_sts, ps->tco2_sts);
+
+	pmc = pmc_mmio_regs();
+	ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
+	ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
+	ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
+	ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
+
+	printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
+		ps->gen_pmcon_a, ps->gen_pmcon_b);
+
+	printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
+		ps->gblrst_cause[0], ps->gblrst_cause[1]);
+}
diff --git a/src/soc/intel/icelake/romstage/Makefile.inc b/src/soc/intel/icelake/romstage/Makefile.inc
index 9fc199deee..28e7eada55 100644
--- a/src/soc/intel/icelake/romstage/Makefile.inc
+++ b/src/soc/intel/icelake/romstage/Makefile.inc
@@ -14,6 +14,5 @@
 #
 
 romstage-y += fsp_params.c
-romstage-y += power_state.c
 romstage-y += romstage.c
 romstage-y += systemagent.c
diff --git a/src/soc/intel/icelake/romstage/power_state.c b/src/soc/intel/icelake/romstage/power_state.c
deleted file mode 100644
index 40775509e4..0000000000
--- a/src/soc/intel/icelake/romstage/power_state.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/mmio.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <intelblocks/pmclib.h>
-#include <intelblocks/tco.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-
-static inline int deep_s3_enabled(void)
-{
-	uint32_t deep_s3_pol;
-
-	deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
-	return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
-}
-
-/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int soc_prev_sleep_state(const struct chipset_power_state *ps,
-	int prev_sleep_state)
-{
-
-	/*
-	 * Check for any power failure to determine if this a wake from
-	* S5 because the PCH does not set the WAK_STS bit when waking
-	* from a true G3 state.
-	*/
-	if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
-		prev_sleep_state = ACPI_S5;
-
-	/*
-	 * If waking from S3 determine if deep S3 is enabled. If not,
-	 * need to check both deep sleep well and normal suspend well.
-	 * Otherwise just check deep sleep well.
-	 */
-	if (prev_sleep_state == ACPI_S3) {
-		/* PWR_FLR represents deep sleep power well loss. */
-		uint32_t mask = PWR_FLR;
-
-		/* If deep s3 isn't enabled check the suspend well too. */
-		if (!deep_s3_enabled())
-			mask |= SUS_PWR_FLR;
-
-		if (ps->gen_pmcon_b & mask)
-			prev_sleep_state = ACPI_S5;
-	}
-
-	return prev_sleep_state;
-}
-
-void soc_fill_power_state(struct chipset_power_state *ps)
-{
-	uint8_t *pmc;
-
-	ps->tco1_sts = tco_read_reg(TCO1_STS);
-	ps->tco2_sts = tco_read_reg(TCO2_STS);
-
-	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n",
-	ps->tco1_sts, ps->tco2_sts);
-
-	pmc = pmc_mmio_regs();
-	ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
-	ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
-	ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
-	ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
-
-	printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
-		ps->gen_pmcon_a, ps->gen_pmcon_b);
-
-	printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
-		ps->gblrst_cause[0], ps->gblrst_cause[1]);
-}