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| author | David Imhoff <dimhoff_devel@xs4all.nl> | 2015-05-06 21:42:37 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-23 22:20:10 +0200 |
| commit | 6b0933adf71fc5ce234e9fd924839b6759d06d7c (patch) | |
| tree | ee3f68e55fd09b49acb3343fb966dcd5c2151399 | |
| parent | dfb53ef0a572576651b43609c981c811d6473668 (diff) | |
| download | coreboot-6b0933adf71fc5ce234e9fd924839b6759d06d7c.tar.xz | |
intel/fsp_baytrail: Fix logging of ISPEnable option
Before this fix the value of PcdEnableSdio was printed as the MIPI/ISP
configuration option.
TEST=Built and booted on Minnowboard Max
Change-Id: Ia9b02d520f4e615f90b45935456b9d97c5d00f11
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10126
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
| -rwxr-xr-x | src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index ad85c5b8a5..7e17f62811 100755 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -173,14 +173,14 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { UpdData->ISPEnable = dev->enabled; } else { - /* Gold2 and earlier FSP: ISPEnable is the filed */ + /* Gold2 and earlier FSP: ISPEnable is the field */ /* next to PcdGttSize in UPD_DATA_REGION struct */ *(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled; printk (FSP_INFO_LEVEL, "Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n"); } printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n", - UpdData->PcdEnableSdio?"Enabled":"Disabled"); + dev->enabled?"Enabled":"Disabled"); break; case EMMC_DEV_FUNC: /* EMMC 4.1*/ if ((dev->enabled) && |