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authorSubrata Banik <subrata.banik@intel.com>2019-05-15 21:23:18 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-05-20 14:50:16 +0000
commit76a8f9e29f3cb6aa2e971957eec7fc05abaf50b8 (patch)
treecd1c89bb0a29d00daef14dcc9418f5931eeac128
parentdd5fa024260bf6fd19c077d640c34e27b742115b (diff)
downloadcoreboot-76a8f9e29f3cb6aa2e971957eec7fc05abaf50b8.tar.xz
soc/intel/cannonlake: Make use of gpio_pm_configure()
Provide option in chip.h to set dynamic local clock gating setting. BUG=b:130764684 TEST=Able to build and boot CML. Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/soc/intel/cannonlake/chip.c23
-rw-r--r--src/soc/intel/cannonlake/chip.h19
-rw-r--r--src/soc/intel/cannonlake/gpio.c21
-rw-r--r--src/soc/intel/cannonlake/gpio_cnp_h.c19
-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h8
-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h7
6 files changed, 86 insertions, 11 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 1bd34c34e0..faddbd5a24 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -166,6 +166,27 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads)
gpio_configure_pads(cfg, num_pads);
}
+/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */
+static void soc_fill_gpio_pm_configuration(void)
+{
+ uint8_t value[TOTAL_GPIO_COMM];
+ const struct device *dev;
+ dev = pcidev_on_root(SA_DEV_SLOT_ROOT, 0);
+ if (!dev || !dev->chip_info)
+ return;
+
+ const config_t *config = dev->chip_info;
+
+ if (config->gpio_override_pm)
+ memcpy(value, config->gpio_pm, sizeof(uint8_t) *
+ TOTAL_GPIO_COMM);
+ else
+ memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+ TOTAL_GPIO_COMM);
+
+ gpio_pm_configure(value, TOTAL_GPIO_COMM);
+}
+
void soc_init_pre_device(void *chip_info)
{
/* Perform silicon specific init. */
@@ -176,6 +197,8 @@ void soc_init_pre_device(void *chip_info)
/* TODO(furquan): Get rid of this workaround once FSP is fixed. */
cnl_configure_pads(NULL, 0);
+
+ soc_fill_gpio_pm_configuration();
}
static void pci_domain_set_resources(struct device *dev)
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2b2a51f6a0..0d51c1ca5c 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -20,6 +20,7 @@
#include <intelblocks/chip.h>
#include <drivers/i2c/designware/dw_i2c.h>
+#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
#include <smbios.h>
#include <stdint.h>
@@ -402,6 +403,24 @@ struct soc_intel_cannonlake_config {
/* Enable GBE wakeup */
uint8_t LanWakeFromDeepSx;
uint8_t WolEnableOverride;
+
+ /*
+ * Override GPIO PM configuration:
+ * 0: Use FSP default GPIO PM program,
+ * 1: coreboot to override GPIO PM program
+ */
+ uint8_t gpio_override_pm;
+ /*
+ * GPIO PM configuration: 0 to disable, 1 to enable power gating
+ * Bit 6-7: Reserved
+ * Bit 5: MISCCFG_GPSIDEDPCGEN
+ * Bit 4: MISCCFG_GPRCOMPCDLCGEN
+ * Bit 3: MISCCFG_GPRTCDLCGEN
+ * Bit 2: MISCCFG_GSXLCGEN
+ * Bit 1: MISCCFG_GPDPCGEN
+ * Bit 0: MISCCFG_GPDLCGEN
+ */
+ uint8_t gpio_pm[TOTAL_GPIO_COMM];
};
typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c
index dd514643d7..4036fdc073 100644
--- a/src/soc/intel/cannonlake/gpio.c
+++ b/src/soc/intel/cannonlake/gpio.c
@@ -77,8 +77,9 @@ static const struct pad_group cnl_community4_groups[] = {
INTEL_GPP(GPP_C0, GPIO_RSVD_22, GPIO_RSVD_27), /* HVMOS */
};
-static const struct pad_community cnl_communities[] = {
- { /* GPP A, B, G, SPI */
+static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
+ /* GPP A, B, G, SPI */
+ [COMM_0] = {
.port = PID_GPIOCOM0,
.first_pad = GPP_A0,
.last_pad = GPIO_RSVD_11,
@@ -96,7 +97,9 @@ static const struct pad_community cnl_communities[] = {
.num_reset_vals = ARRAY_SIZE(rst_map_com0),
.groups = cnl_community0_groups,
.num_groups = ARRAY_SIZE(cnl_community0_groups),
- }, { /* GPP D, F, H, VGPIO */
+ },
+ /* GPP D, F, H, VGPIO */
+ [COMM_1] = {
.port = PID_GPIOCOM1,
.first_pad = GPP_D0,
.last_pad = vSD3_CD_B,
@@ -114,7 +117,9 @@ static const struct pad_community cnl_communities[] = {
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = cnl_community1_groups,
.num_groups = ARRAY_SIZE(cnl_community1_groups),
- }, { /* GPD */
+ },
+ /* GPD */
+ [COMM_2] = {
.port = PID_GPIOCOM2,
.first_pad = GPD0,
.last_pad = GPD11,
@@ -132,7 +137,9 @@ static const struct pad_community cnl_communities[] = {
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = cnl_community2_groups,
.num_groups = ARRAY_SIZE(cnl_community2_groups),
- }, { /* AZA, CPU */
+ },
+ /* AZA, CPU */
+ [COMM_3] = {
.port = PID_GPIOCOM3,
.first_pad = HDA_BCLK,
.last_pad = GPIO_RSVD_38,
@@ -150,7 +157,9 @@ static const struct pad_community cnl_communities[] = {
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = cnl_community3_groups,
.num_groups = ARRAY_SIZE(cnl_community3_groups),
- }, { /* GPP C, E, JTAG, HVMOS */
+ },
+ /* GPP C, E, JTAG, HVMOS */
+ [COMM_4] = {
.port = PID_GPIOCOM4,
.first_pad = GPP_C0,
.last_pad = GPIO_RSVD_27,
diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c
index 102444a9f8..dd9f433645 100644
--- a/src/soc/intel/cannonlake/gpio_cnp_h.c
+++ b/src/soc/intel/cannonlake/gpio_cnp_h.c
@@ -80,7 +80,8 @@ static const struct pad_group cnl_community4_groups[] = {
};
static const struct pad_community cnl_communities[] = {
- { /* GPP A, B */
+ /* GPP A, B */
+ [COMM_0] = {
.port = PID_GPIOCOM0,
.first_pad = GPP_A0,
.last_pad = GPIO_RSVD_2,
@@ -98,7 +99,9 @@ static const struct pad_community cnl_communities[] = {
.num_reset_vals = ARRAY_SIZE(rst_map_com0),
.groups = cnl_community0_groups,
.num_groups = ARRAY_SIZE(cnl_community0_groups),
- }, { /* GPP C, D, G */
+ },
+ /* GPP C, D, G */
+ [COMM_1] = {
.port = PID_GPIOCOM1,
.first_pad = GPP_C0,
.last_pad = vSSP2_RXD,
@@ -116,7 +119,9 @@ static const struct pad_community cnl_communities[] = {
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = cnl_community1_groups,
.num_groups = ARRAY_SIZE(cnl_community1_groups),
- }, { /* GPD */
+ },
+ /* GPD */
+ [COMM_2] = {
.port = PID_GPIOCOM2,
.first_pad = GPD0,
.last_pad = GPD11,
@@ -134,7 +139,9 @@ static const struct pad_community cnl_communities[] = {
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = cnl_community2_groups,
.num_groups = ARRAY_SIZE(cnl_community2_groups),
- }, { /* GPP K, H, E, F */
+ },
+ /* GPP K, H, E, F */
+ [COMM_3] = {
.port = PID_GPIOCOM3,
.first_pad = GPP_K0,
.last_pad = GPIO_RSVD_19,
@@ -152,7 +159,9 @@ static const struct pad_community cnl_communities[] = {
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = cnl_community3_groups,
.num_groups = ARRAY_SIZE(cnl_community3_groups),
- }, { /* GPP I, J */
+ },
+ /* GPP I, J */
+ [COMM_4] = {
.port = PID_GPIOCOM4,
.first_pad = GPIO_RSVD_20,
.last_pad = GPP_J11,
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
index 59901440d9..698bd2a5c7 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
@@ -355,4 +355,12 @@
#define TOTAL_PADS 275
#define SD_PWR_EN_PIN GPP_A17
+
+#define COMM_0 0
+#define COMM_1 1
+#define COMM_2 2
+#define COMM_3 3
+#define COMM_4 4
+#define TOTAL_GPIO_COMM 5
+
#endif
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
index 1788e78989..5176ac734a 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
@@ -399,4 +399,11 @@
#define TOTAL_PADS (GPD11 + 1)
+#define COMM_0 0
+#define COMM_1 1
+#define COMM_2 2
+#define COMM_3 3
+#define COMM_4 4
+#define TOTAL_GPIO_COMM 5
+
#endif