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authorPatrick Rudolph <patrick.rudolph@9elements.com>2018-09-28 11:33:16 +0200
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-09-30 03:04:53 +0000
commit7de4bb5172134fb801d0c087a84013b58b35d9d2 (patch)
treed8b84d59506d13a7a73b3fc7f83741686893aa61
parent61452a11e23c00c978e182af4ad1e6d958fb6db2 (diff)
downloadcoreboot-7de4bb5172134fb801d0c087a84013b58b35d9d2.tar.xz
soc/cavium/cn81xx/spi: Add function to return SPI clock
Change-Id: I07c95b9ea14d47da0497470487fa3f162f8012c8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
-rw-r--r--src/soc/cavium/cn81xx/include/soc/spi.h1
-rw-r--r--src/soc/cavium/cn81xx/spi.c21
2 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/cavium/cn81xx/include/soc/spi.h b/src/soc/cavium/cn81xx/include/soc/spi.h
index bb69daac91..33f0f2988b 100644
--- a/src/soc/cavium/cn81xx/include/soc/spi.h
+++ b/src/soc/cavium/cn81xx/include/soc/spi.h
@@ -29,6 +29,7 @@ void spi_set_clock(const size_t bus,
const size_t speed_hz,
const size_t idle_low,
const size_t idle_cycles);
+uint64_t spi_get_clock(const size_t bus);
void spi_set_lsbmsb(const size_t bus, const size_t lsb_first);
void spi_init_custom(const size_t bus,
const size_t speed_hz,
diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c
index 5a5865e36e..6527f22ea1 100644
--- a/src/soc/cavium/cn81xx/spi.c
+++ b/src/soc/cavium/cn81xx/spi.c
@@ -218,6 +218,27 @@ void spi_set_clock(const size_t bus,
}
/**
+ * Get current SPI clock frequency in Hz.
+ *
+ * @param bus The SPI bus to operate on
+ */
+uint64_t spi_get_clock(const size_t bus)
+{
+ union cavium_spi_cfg cfg;
+
+ assert(bus < ARRAY_SIZE(cavium_spi_slaves));
+ if (bus >= ARRAY_SIZE(cavium_spi_slaves))
+ return 0;
+
+ struct cavium_spi *regs = cavium_spi_slaves[bus].regs;
+ const uint64_t sclk = thunderx_get_io_clock();
+
+ cfg.u = read64(&regs->cfg);
+
+ return (sclk / (2ULL * cfg.s.clkdiv));
+}
+
+/**
* Set SPI LSB/MSB first.
*
* @param bus The SPI bus to operate on