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authorGabe Black <gabeblack@google.com>2013-09-29 06:32:27 -0700
committerIsaac Christensen <isaac.christensen@se-eng.com>2014-08-28 01:24:12 +0200
commit7f0747562ed43b8461aae6960f2615d2b84b6387 (patch)
tree2ecb9933fcf334f8dc51ff5e38f55396b2edc196
parenta2a87d4bca39bdb2e0ffda88e50cab0a98a09621 (diff)
downloadcoreboot-7f0747562ed43b8461aae6960f2615d2b84b6387.tar.xz
tegra124: Add a custom bootblock implementation.
This implementation is the same as the general one except that it removes all the things that don't work on an ARMv4. Change-Id: I1108a79cc656b26f7d48df20aef3016cf5ae3182 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171019 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d1436288d3b025af27a8d28ba94b589940ead504) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6713 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
-rw-r--r--src/soc/nvidia/tegra124/Kconfig2
-rw-r--r--src/soc/nvidia/tegra124/Makefile.inc4
-rw-r--r--src/soc/nvidia/tegra124/bootblock.c16
-rw-r--r--src/soc/nvidia/tegra124/bootblock_asm.S98
4 files changed, 117 insertions, 3 deletions
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig
index 10a65f7ccc..7f03ad71ce 100644
--- a/src/soc/nvidia/tegra124/Kconfig
+++ b/src/soc/nvidia/tegra124/Kconfig
@@ -2,9 +2,9 @@ config SOC_NVIDIA_TEGRA124
select ARCH_BOOTBLOCK_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
+ select ARM_BOOTBLOCK_CUSTOM
bool
default n
- select CPU_HAS_BOOTBLOCK_INIT
if SOC_NVIDIA_TEGRA124
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index 9f9009d0b4..c7d56ab114 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -1,6 +1,10 @@
CBOOTIMAGE = cbootimage
+bootblock-c-ccopts += -marm
+bootblock-S-ccopts += -marm
+
bootblock-y += bootblock.c
+bootblock-y += bootblock_asm.S
bootblock-y += cbfs.c
bootblock-y += clock.c
bootblock-y += i2c.c
diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c
index 66e6b3b6da..97180a0a33 100644
--- a/src/soc/nvidia/tegra124/bootblock.c
+++ b/src/soc/nvidia/tegra124/bootblock.c
@@ -17,8 +17,20 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <bootblock_common.h>
+#include <arch/hlt.h>
+#include <arch/stages.h>
+#include <cbfs.h>
+#include <console/console.h>
-void bootblock_cpu_init(void)
+void main(void)
{
+ void *entry;
+
+ if (CONFIG_BOOTBLOCK_CONSOLE)
+ console_init();
+
+ entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage");
+
+ if (entry) stage_exit(entry);
+ hlt();
}
diff --git a/src/soc/nvidia/tegra124/bootblock_asm.S b/src/soc/nvidia/tegra124/bootblock_asm.S
new file mode 100644
index 0000000000..8d0beb8711
--- /dev/null
+++ b/src/soc/nvidia/tegra124/bootblock_asm.S
@@ -0,0 +1,98 @@
+/*
+ * Early initialization code for ARMv7 architecture.
+ *
+ * This file is based off of the OMAP3530/ARM Cortex start.S file from Das
+ * U-Boot, which itself got the file from armboot.
+ *
+ * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
+ * Copyright (c) 2013 The Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.section ".start", "a", %progbits
+.globl _start
+_start: b reset
+ .balignl 16,0xdeadbeef
+
+_cbfs_master_header:
+ /* The CBFS master header is inserted by cbfstool at the first
+ * aligned offset after the above anchor string is found.
+ * Hence, we leave some space for it.
+ */
+ .skip 128 @ Assumes 64-byte alignment
+
+reset:
+ /*
+ * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
+ * aborts may happen early and crash before the abort handlers are
+ * installed, but at least the problem will show up near the code that
+ * causes it.
+ */
+ msr cpsr_cxf, #0xdf
+
+ /*
+ * Initialize the stack to a known value. This is used to check for
+ * stack overflow later in the boot process.
+ */
+ ldr r0, .Stack
+ ldr r1, .Stack_size
+ sub r0, r0, r1
+ ldr r1, .Stack
+ ldr r2, =0xdeadbeef
+init_stack_loop:
+ str r2, [r0]
+ add r0, #4
+ cmp r0, r1
+ bne init_stack_loop
+
+/* Set stackpointer in internal RAM to call board_init_f */
+call_bootblock:
+ ldr sp, .Stack /* Set up stack pointer */
+ ldr r0,=0x00000000
+ /*
+ * The current design of cpu_info places the
+ * struct at the top of the stack. The number of
+ * words pushed must be at least as large as that
+ * struct.
+ */
+ push {r0-r2}
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+ /*
+ * Use "bl" instead of "b" even though we do not intend to return.
+ * "bl" gets compiled to "blx" if we're transitioning from ARM to
+ * Thumb. However, "b" will not and GCC may attempt to create a
+ * wrapper which is currently broken.
+ */
+ bl main
+
+/* we do it this way because it's a 32-bit constant and
+ * in some cases too far away to be loaded as just an offset
+ * from IP
+ */
+.align 2
+.Stack:
+ .word CONFIG_STACK_TOP
+.align 2
+/* create this size the same way we do in coreboot_ram.ld: top-bottom */
+.Stack_size:
+ .word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM