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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-03-05 00:54:02 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-06 17:24:26 +0000
commit8488853fab0417b222ae04924574bd6f2221ca0e (patch)
treefa2766560a44948ca50bee3f5c9ad8588e6a5751
parentdbc958495d3b7c94046b3b8f826f9316ee528e48 (diff)
downloadcoreboot-8488853fab0417b222ae04924574bd6f2221ca0e.tar.xz
soc/intel/tigerlake: Enable CNVi Mode
Add configs to enable CNVi mode and CNViBtCore. BUG=none BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ic372348a1409b2594a85b71b2fc742be96b84b87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39317 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/tigerlake/chip.h4
-rw-r--r--src/soc/intel/tigerlake/fsp_params_tgl.c4
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index e57abe857b..a6bcf0847f 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -208,6 +208,10 @@ struct soc_intel_tigerlake_config {
/* Enable Pch iSCLK */
uint8_t pch_isclk;
+ /* CNVi */
+ uint8_t CnviMode;
+ uint8_t CnviBtCore;
+
/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
enum {
FORCE_DISABLE,
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 9e22b58e7c..0dae0fed47 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -149,6 +149,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
else
params->PchLanEnable = dev->enabled;
+ /* CNVi */
+ params->CnviMode = config->CnviMode;
+ params->CnviBtCore = config->CnviBtCore;
+
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;