[REMOVAL] tyan/s2895

As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I9099f90c073197cc95bb9630788016b7b8221922
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12383
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

13 files changed, 0 insertions, 1698 deletions

diff --git a/src/mainboard/tyan/s2895/Kconfig b/src/mainboard/tyan/s2895/Kconfig
deleted file mode 100644
index 21db63ccaf..0000000000
--- a/src/mainboard/tyan/s2895/Kconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-if BOARD_TYAN_S2895
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_AMD_SOCKET_940
-	select NORTHBRIDGE_AMD_AMDK8
-	select SOUTHBRIDGE_NVIDIA_CK804
-	select SOUTHBRIDGE_AMD_AMD8131
-	select HT_CHAIN_DISTRIBUTE
-	select SUPERIO_SMSC_LPC47B397
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_1024
-	select QRANK_DIMM_SUPPORT
-	select K8_ALLOCATE_IO_RANGE
-
-config MAINBOARD_DIR
-	string
-	default tyan/s2895
-
-config APIC_ID_OFFSET
-	hex
-	default 0x10
-
-config CK804_NUM
-	int
-	default 2
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "S2895"
-
-config MAX_CPUS
-	int
-	default 4
-
-config MAX_PHYSICAL_CPUS
-	int
-	default 2
-
-config HT_CHAIN_UNITID_BASE
-	hex
-	default 0
-
-config HT_CHAIN_END_UNITID_BASE
-	hex
-	default 0x20
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-endif # BOARD_TYAN_S2895
diff --git a/src/mainboard/tyan/s2895/Kconfig.name b/src/mainboard/tyan/s2895/Kconfig.name
deleted file mode 100644
index ff55226cee..0000000000
--- a/src/mainboard/tyan/s2895/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_TYAN_S2895
-	bool "S2895 (Thunder K8WE)"
diff --git a/src/mainboard/tyan/s2895/acpi_tables.c b/src/mainboard/tyan/s2895/acpi_tables.c
deleted file mode 100644
index d66a5de54b..0000000000
--- a/src/mainboard/tyan/s2895/acpi_tables.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Island Aruma ACPI support
- * written by Stefan Reinauer <stepan@openbios.org>
- *  (C) 2005 Stefan Reinauer
- *
- *
- *  Copyright 2005 AMD
- *  2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include <cpu/amd/powernow.h>
-
-/* APIC */
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	unsigned long apic_addr;
-	device_t dev;
-	struct resource *res;
-
-	get_bus_conf();
-
-	/* create all subtables for processors */
-	current = acpi_create_madt_lapics(current);
-
-	/* Write NVIDIA CK804 IOAPIC. */
-	dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
-	ASSERT(dev != NULL);
-
-	res = find_resource(dev, PCI_BASE_ADDRESS_1);
-	ASSERT(res != NULL);
-
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4,
-					   res->base, 0);
-	/* Initialize interrupt mapping if mptable.c didn't. */
-#if (!CONFIG_GENERATE_MP_TABLE)
-	pci_write_config32(dev, 0x7c, 0x0120d218);
-	pci_write_config32(dev, 0x80, 0x12008a00);
-	pci_write_config32(dev, 0x84, 0x00080d7d);
-#endif
-
-	/* Write AMD 8131 two IOAPICs. */
-	dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1));
-	if (dev) {
-		apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf;
-		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5,
-						   apic_addr, 0x18);
-	}
-
-	dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1));
-	if (dev) {
-		apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf;
-		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6,
-						   apic_addr, 0x1C);
-	}
-
-	/* Write second NVIDIA CK804 IOAPIC. */
-	dev = dev_find_slot(0x80, PCI_DEVFN(0x1, 0));
-	ASSERT(dev != NULL);
-
-	res = find_resource(dev, PCI_BASE_ADDRESS_1);
-	ASSERT(res != NULL);
-
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 7,
-					   res->base, 0x20);
-	/* Initialize interrupt mapping if mptable.c didn't. */
-#if (!CONFIG_GENERATE_MP_TABLE)
-	pci_write_config32(dev, 0x7c, 0x0000d218); // Why does the factory BIOS have 0?
-	pci_write_config32(dev, 0x80, 0x00000000);
-	pci_write_config32(dev, 0x84, 0x00000d00); // Same here.
-#endif
-
-	/* IRQ9 */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		current, 0, 9, 9, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW);
-
-	/* IRQ0 -> APIC IRQ2. */
-	/* Doesn't work on this board. */
-
-	/* 0: mean bus 0--->ISA */
-	/* 0: PIC 0 */
-	/* 2: APIC 2 */
-	/* 5 mean: 0101 --> Edge-triggered, Active high */
-
-	/* create all subtables for processors */
-	/* acpi_create_madt_lapic_nmis returns current, not size. */
-	current = acpi_create_madt_lapic_nmis(current, 5, 1);
-
-	return current;
-}
diff --git a/src/mainboard/tyan/s2895/board_info.txt b/src/mainboard/tyan/s2895/board_info.txt
deleted file mode 100644
index ba138fd3e4..0000000000
--- a/src/mainboard/tyan/s2895/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Board name: Thunder K8WE (S2895)
-Category: desktop
-Board URL: http://www.tyan.com/archive/products/html/thunderk8we.html
-Release year: 2005
diff --git a/src/mainboard/tyan/s2895/cmos.layout b/src/mainboard/tyan/s2895/cmos.layout
deleted file mode 100644
index 4e081ea1aa..0000000000
--- a/src/mainboard/tyan/s2895/cmos.layout
+++ /dev/null
@@ -1,60 +0,0 @@
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       r       0        reboot_bits
-392          3       e       5        baud_rate
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399          1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-456          1       e       1        ECC_memory
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-5     0     115200
-5     1     57600
-5     2     38400
-5     3     19200
-5     4     9600
-5     5     4800
-5     6     2400
-5     7     1200
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-8     0     DDR400
-8     1     DDR333
-8     2     DDR266
-8     3     DDR200
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/tyan/s2895/devicetree.cb b/src/mainboard/tyan/s2895/devicetree.cb
deleted file mode 100644
index 4250160b15..0000000000
--- a/src/mainboard/tyan/s2895/devicetree.cb
+++ /dev/null
@@ -1,153 +0,0 @@
-chip northbridge/amd/amdk8/root_complex		# Root complex
-  device cpu_cluster 0 on			# (L)APIC cluster
-    chip cpu/amd/socket_940			# CPU socket
-      device lapic 0 on end			# Local APIC of the CPU
-    end
-  end
-  device domain 0 on			# PCI domain
-    subsystemid 0x10f1 0x2895 inherit
-    chip northbridge/amd/amdk8			# Northbridge / RAM controller
-      device pci 18.0 on			# Link 0 == LDT 0
-        chip southbridge/nvidia/ck804		# Southbridge
-          device pci 0.0 on end			# HT
-          device pci 1.0 on			# LPC
-            chip superio/smsc/lpc47b397		# Super I/O
-              device pnp 2e.0 on		# Floppy
-                io 0x60 = 0x3f0
-                irq 0x70 = 6
-                drq 0x74 = 2
-              end
-              device pnp 2e.3 on		# Parallel port
-                io 0x60 = 0x378
-                irq 0x70 = 7
-                drq 0x74 = 4
-              end
-              device pnp 2e.4 on		# Com1
-                io 0x60 = 0x3f8
-                irq 0x70 = 4
-              end
-              device pnp 2e.5 off		# Com2
-                io 0x60 = 0x2f8
-                irq 0x70 = 3
-              end
-              device pnp 2e.7 on		# PS/2 keyboard & mouse
-                io 0x60 = 0x60
-                io 0x62 = 0x64
-                irq 0x70 = 1
-                irq 0x72 = 12
-              end
-              device pnp 2e.8 on		# Hardware monitor
-                io 0x60 = 0x480
-                chip drivers/generic/generic	# LM95221 CPU temp
-                  device i2c 2b on end
-                end
-                chip drivers/generic/generic	# EMCT03
-                  device i2c 54 on end
-                end
-              end
-              device pnp 2e.a on		# RT
-                io 0x60 = 0x400
-              end
-            end
-          end
-          device pci 1.1 on			# SM 0
-            chip drivers/generic/generic	# DIMM 0-0-0
-              device i2c 50 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-0-1
-              device i2c 51 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-0
-              device i2c 52 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-1
-              device i2c 53 on end
-            end
-            chip drivers/generic/generic	# DIMM 1-0-0
-              device i2c 54 on end
-            end
-            chip drivers/generic/generic	# DIMM 1-0-1
-              device i2c 55 on end
-            end
-            chip drivers/generic/generic	# DIMM 1-1-0
-              device i2c 56 on end
-            end
-            chip drivers/generic/generic	# DIMM 1-1-1
-              device i2c 57 on end
-            end
-          end
-          device pci 1.1 on			# SM 1
-            chip drivers/generic/generic	# MAC EEPROM
-              device i2c 51 on end
-            end
-          end
-          device pci 2.0 on end			# USB 1.1
-          device pci 2.1 on end			# USB 2
-          device pci 4.0 on end			# ACI
-          device pci 4.1 off end		# MCI
-          device pci 6.0 on end			# IDE
-          device pci 7.0 on end			# SATA 1
-          device pci 8.0 on end			# SATA 0
-          device pci 9.0 on end			# PCI
-          device pci a.0 on end			# NIC
-          device pci b.0 off end		# PCI E 3
-          device pci c.0 off end		# PCI E 2
-          device pci d.0 off end		# PCI E 1
-          device pci e.0 on end			# PCI E 0
-          register "ide0_enable" = "1"
-          register "ide1_enable" = "1"
-          register "sata0_enable" = "1"
-          register "sata1_enable" = "1"
-          # 1: SMBus under 2e.8, 2: SM0 3: SM1
-          register "mac_eeprom_smbus" = "3"
-          register "mac_eeprom_addr" = "0x51"
-        end
-      end
-      device pci 18.0 on end			# Link 1
-      device pci 18.0 on			# Link 2 == LDT 2
-        chip southbridge/amd/amd8131		# Southbridge
-          device pci 0.0 on end
-          device pci 0.1 on end
-          device pci 1.0 on
-            device pci 6.0 on end		# LSI SCSI
-            device pci 6.1 on end
-          end
-          device pci 1.1 on end
-        end
-      end
-      device pci 18.1 on end
-      device pci 18.2 on end
-      device pci 18.3 on end
-    end
-    chip northbridge/amd/amdk8			# Northbridge / RAM controller
-      device pci 19.0 on			# Link 0 == LDT 0
-        chip southbridge/nvidia/ck804		# Southbridge
-          device pci 0.0 on end			# HT
-          device pci 1.0 on end			# LPC
-          device pci 1.1 off end		# SM
-          device pci 2.0 off end		# USB 1.1
-          device pci 2.1 off end		# USB 2
-          device pci 4.0 off end		# ACI
-          device pci 4.1 off end		# MCI
-          device pci 6.0 off end		# IDE
-          device pci 7.0 off end		# SATA 1
-          device pci 8.0 off end		# SATA 0
-          device pci 9.0 off end		# PCI
-          device pci a.0 on end			# NIC
-          device pci b.0 off end		# PCI E 3
-          device pci c.0 off end		# PCI E 2
-          device pci d.0 off end		# PCI E 1
-          device pci e.0 on end			# PCI E 0
-          # 1: SMBus under 2e.8, 2: SM0 3: SM1
-          register "mac_eeprom_smbus" = "3"
-          register "mac_eeprom_addr" = "0x51"
-        end
-      end
-      device pci 19.0 on end
-      device pci 19.0 on end
-      device pci 19.1 on end
-      device pci 19.2 on end
-      device pci 19.3 on end
-    end
-  end
-end
diff --git a/src/mainboard/tyan/s2895/dsdt.asl b/src/mainboard/tyan/s2895/dsdt.asl
deleted file mode 100644
index ef6f4cbf3f..0000000000
--- a/src/mainboard/tyan/s2895/dsdt.asl
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE  ", "CB-DSDT ", 1)
-{
-	 #include "northbridge/amd/amdk8/util.asl"
-
-	/* For now only define 2 power states:
-	 *  - S0 which is fully on
-	 *  - S5 which is soft off
-	 * Any others would involve declaring the wake up methods.
-	 */
-	Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
-	Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
-
-	/* Root of the bus hierarchy */
-	Scope (\_SB)
-	{
-		/* Top PCI device (CK804) */
-		Device (PCI0)
-		{
-			Name (_HID, EisaId ("PNP0A03"))
-			Name (_ADR, 0x00)
-			Name (_UID, 0x00)
-			Name (_BBN, 0x00)
-
-			External (BUSN)
-			External (MMIO)
-			External (PCIO)
-			External (SBLK)
-			External (TOM1)
-			External (HCLK)
-			External (SBDN)
-			External (HCDN)
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate ()
-				{
-					IO (Decode16,
-					0x0CF8,	// Address Range Minimum
-					0x0CF8,	// Address Range Maximum
-					0x01,	// Address Alignment
-					0x08,	// Address Length
-					)
-					WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,	// Address Space Granularity
-					0x0000,	// Address Range Minimum
-					0x0CF7,	// Address Range Maximum
-					0x0000,	// Address Translation Offset
-					0x0CF8,	// Address Length
-					,, , TypeStatic)
-				})
-				/* Methods bellow use SSDT to get actual MMIO regs
-				   The IO ports are from 0xd00, optionally an VGA,
-				   otherwise the info from MMIO is used.
-				   \_SB.GXXX(node, link)
-				 */
-				Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
-				Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
-				Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
-				Return (Local3)
-			}
-
-			/* PCI Routing Table */
-			Name (_PRT, Package () {
-						/* Since source is 0, index is IRQ. */
-						/* in ABCD, A=0, B=1, C=2, D=3 */
-						/* SlotFFFF, ABCD, source, index */
-				Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */
-				Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */
-				Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */
-				Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x14 }, /* 0x2 AUDIO IRQ 20 */
-				Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */
-				Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */
-				Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x15 }, /* 0xa LAN IRQ 21 */
-			})
-
-			Device (PCIL)
-			{
-				Name (_ADR, 0x00090000)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x01)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, /* 1:04 PCI 32 IRQ16-IRQ19 */
-					Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
-					Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
-					Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
-					Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x13 }, /* 1:05 IEEE-1394 IRQ 19 */
-				})
-			}
-
-			/* 2:00 PCIe x16 SB IRQ 18 */
-			Device (PE16)
-			{
-				Name (_ADR, 0x000e0000)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x02)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
-				})
-			}
-
-			Device (ISA) {
-				Name (_HID, EisaId ("PNP0A05"))
-				Name (_ADR, 0x00010000)
-
-				/* PS/2 keyboard (seems to be important for WinXP install) */
-				Device (KBD)
-				{
-					Name (_HID, EisaId ("PNP0303"))
-					Method (_STA, 0, NotSerialized)
-					{
-						Return (0x0f)
-					}
-					Method (_CRS, 0, NotSerialized)
-					{
-						Name (TMP, ResourceTemplate () {
-							IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
-							IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
-							IRQNoFlags () {1}
-						})
-						Return (TMP)
-					}
-				}
-
-				/* PS/2 mouse */
-				Device (MOU)
-				{
-					Name (_HID, EisaId ("PNP0F13"))
-					Method (_STA, 0, NotSerialized)
-					{
-						Return (0x0f)
-					}
-					Method (_CRS, 0, NotSerialized)
-					{
-						Name (TMP, ResourceTemplate () {
-							IRQNoFlags () {12}
-						})
-						Return (TMP)
-					}
-				}
-
-				/* Parallel port */
-				Device (LP0)
-				{
-					Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
-					Method (_STA, 0, NotSerialized)
-					{
-						Return (0x0f)
-					}
-					Method (_CRS, 0, NotSerialized)
-					{
-						Name (TMP, ResourceTemplate () {
-							FixedIO (0x0378, 0x10)
-							IRQNoFlags () {7}
-						})
-						Return (TMP)
-					}
-				}
-
-				/* RTC */
-				Device (RTC)
-				{
-					Name (_HID, EisaId ("PNP0B00"))
-					Method (_CRS, 0, NotSerialized)
-					{
-						Name (TMP, ResourceTemplate () {
-							FixedIO (0x0070, 0x02)
-							IRQNoFlags () {8}
-						})
-						Return (TMP)
-					}
-				}
-
-				/* Floppy controller */
-				Device (FDC0)
-				{
-					Name (_HID, EisaId ("PNP0700"))
-					Method (_STA, 0, NotSerialized)
-					{
-						Return (0x0f)
-					}
-					Method (_CRS, 0, NotSerialized)
-					{
-						Name (BUF0, ResourceTemplate () {
-							FixedIO (0x03F0, 0x08)
-							IRQNoFlags () {6}
-							DMA (Compatibility, NotBusMaster, Transfer8) {2}
-						})
-						Return (BUF0)
-					}
-				}
-			}
-		}
-
-		/* CK804 2050 */
-		Device (PCI1)
-		{
-			Name (_HID, EisaId ("PNP0A03"))
-			Name (_ADR, 0x00)
-			Name (_UID, 0x00)
-			Name (_BBN, 0x80)
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate ()
-				{
-					IO (Decode16,
-					0x0CF8,	// Address Range Minimum
-					0x0CF8,	// Address Range Maximum
-					0x01,	// Address Alignment
-					0x08,	// Address Length
-					)
-				})
-				/* Methods bellow use SSDT to get actual MMIO regs
-				   The IO ports are from 0xd00, optionally an VGA,
-				   otherwise the info from MMIO is used.
-				   \_SB.GXXX(node, link)
-				 */
-				Concatenate (\_SB.GMEM (0x01, 0x00), BUF0, Local1)
-				Concatenate (\_SB.GIOR (0x01, 0x00), Local1, Local2)
-				Concatenate (\_SB.GWBN (0x01, 0x00), Local2, Local3)
-				Return (Local3)
-			}
-
-			/* PCI Routing Table for this root bus */
-			Name (_PRT, Package () {
-						/* Since source is 0, index is IRQ. */
-						/* in ABCD, A=0, B=1, C=2, D=3 */
-						/* SlotFFFF, ABCD, source, index */
-				Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x35 }, /* 0xa LAN IRQ 53 */
-			})
-
-			/* PCIe x16 SB2 IRQ 18 */
-			Device (PE16)
-			{
-				Name (_ADR, 0x000e0000)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x81)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x32 }, /* PCIE IRQ48-IRQ51 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x33 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x30 },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x31 },
-				})
-			}
-
-		}
-
-		/* AMD 8131 PCI-X tunnel */
-		Device (PCI2)
-		{
-			Name (_HID, EisaId ("PNP0A03"))
-			Name (_ADR, 0x00)
-			Name (_UID, 0x00)
-			Name (_BBN, 0x40)
-
-			/* There is no _PRT Here because I don't know what to
-			 * put in it.  Since the 8131 has its own APIC, it
-			 * isn't wired to other IRQs. */
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate ()
-				{
-					IO (Decode16,
-					0x0CF8,	// Address Range Minimum
-					0x0CF8,	// Address Range Maximum
-					0x01,	// Address Alignment
-					0x08,	// Address Length
-					)
-				})
-				/* Methods bellow use SSDT to get actual MMIO regs
-				   The IO ports are from 0xd00, optionally an VGA,
-				   otherwise the info from MMIO is used.
-				   \_SB.GXXX(node, link)
-				 */
-				Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1)
-				Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2)
-				Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3)
-				Return (Local3)
-			}
-
-			/* Channel A PCIX 133 */
-			Device (PCXF)
-			{
-				Name (_ADR, 0x00000000)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x41)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
-					Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 },
-					Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1a },
-					Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1b },
-				})
-			}
-
-			/* Channel B PCIX 100 */
-			Device (PCXS) /* Slot 4, Onboard SCSI, Slot 5 */
-			{
-				Name (_ADR, 0x00010000)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x42)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */
-					Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1d },
-					Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1e },
-					Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1f },
-					Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x1e }, /* PCIE IRQ28-IRQ31 shifted 2 */
-					Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x1f },
-					Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1c },
-					Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1d },
-					Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1d }, /* PCIE IRQ28-IRQ31 shifted 1 */
-					Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1e },
-					Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1f },
-					Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1c },
-				})
-			}
-		}
-	}
-}
diff --git a/src/mainboard/tyan/s2895/get_bus_conf.c b/src/mainboard/tyan/s2895/get_bus_conf.c
deleted file mode 100644
index b8881f5078..0000000000
--- a/src/mainboard/tyan/s2895/get_bus_conf.c
+++ /dev/null
@@ -1,168 +0,0 @@
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_ck804_0;	//1
-unsigned char bus_ck804_1;	//2
-unsigned char bus_ck804_2;	//3
-unsigned char bus_ck804_3;	//4
-unsigned char bus_ck804_4;	//5
-unsigned char bus_ck804_5;	//6
-unsigned char bus_8131_0;	//7
-unsigned char bus_8131_1;	//8
-unsigned char bus_8131_2;	//9
-unsigned char bus_ck804b_0;	//a
-unsigned char bus_ck804b_1;	//b
-unsigned char bus_ck804b_2;	//c
-unsigned char bus_ck804b_3;	//d
-unsigned char bus_ck804b_4;	//e
-unsigned char bus_ck804b_5;	//f
-unsigned apicid_ck804;
-unsigned apicid_8131_1;
-unsigned apicid_8131_2;
-unsigned apicid_ck804b;
-
-unsigned pci1234x[] = {		//Here you only need to set value in pci1234 for HT-IO that could be installed or not
-	//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-	0x0000ff0,
-	0x0000ff0,
-	0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0
-};
-
-unsigned hcdnx[] = {		//HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
-	0x20202020,
-	0x20202020,
-	0x20202020,
-//        0x20202020,
-//        0x20202020,
-//        0x20202020,
-//        0x20202020,
-//        0x20202020,
-};
-
-unsigned sbdn3;
-unsigned sbdnb;
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
-	unsigned apicid_base;
-	unsigned sbdn;
-
-	device_t dev;
-	int i;
-
-	if (get_bus_conf_done == 1)
-		return;		//do it only once
-
-	get_bus_conf_done = 1;
-
-	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
-	for (i = 0; i < sysconf.hc_possible_num; i++) {
-		sysconf.pci1234[i] = pci1234x[i];
-		sysconf.hcdn[i] = hcdnx[i];
-	}
-
-	get_sblk_pci1234();
-
-	sysconf.sbdn = (sysconf.hcdn[0] & 0xff);	// first byte of first chain
-	sbdn = sysconf.sbdn;
-
-	sbdn3 = (sysconf.hcdn[1] & 0xff);
-
-	sbdnb = (sysconf.hcdn[2] & 0xff);	// first byte of second chain
-
-	bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff;
-
-	/* CK804 */
-	dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09, 0));
-	if (dev) {
-		bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-		bus_ck804_5++;
-	} else {
-		printk(BIOS_DEBUG,
-		       "ERROR - could not find PCI 1:%02x.0, using defaults\n",
-		       sbdn + 0x09);
-
-		bus_ck804_1 = 2;
-		bus_ck804_5 = 3;
-	}
-
-	dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0e, 0));
-	if (dev) {
-		bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	} else {
-		printk(BIOS_DEBUG,
-		       "ERROR - could not find PCI 1:%02x.0, using defaults\n",
-		       sbdn + 0x0e);
-	}
-
-	bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
-	/* 8131-1 */
-	dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0));
-	if (dev) {
-		bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-		bus_8131_2++;
-	} else {
-		printk(BIOS_DEBUG,
-		       "ERROR - could not find PCI %02x:01.0, using defaults\n",
-		       bus_8131_0);
-
-		bus_8131_1 = bus_8131_0 + 1;
-		bus_8131_2 = bus_8131_0 + 2;
-	}
-	/* 8131-2 */
-	dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0));
-	if (dev) {
-		bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	} else {
-		printk(BIOS_DEBUG,
-		       "ERROR - could not find PCI %02x:02.0, using defaults\n",
-		       bus_8131_0);
-
-		bus_8131_2 = bus_8131_1 + 1;
-	}
-
-	/* CK804b */
-
-	if (sysconf.pci1234[2] & 0x0f) {	//if the second cpu is installed
-		bus_ck804b_0 = (sysconf.pci1234[2] >> 16) & 0xff;
-
-		dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e, 0));
-		if (dev) {
-			bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		} else {
-			printk(BIOS_DEBUG,
-			       "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
-			       bus_ck804b_0, sbdnb + 0x0e);
-			bus_ck804b_5 = bus_ck804b_4 + 1;
-		}
-	}
-
-/*I/O APICs:	APIC ID	Version	State		Address*/
-	if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
-		apicid_base = get_apicid_base(4);
-	else
-		apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
-	apicid_ck804 = apicid_base + 0;
-	apicid_8131_1 = apicid_base + 1;
-	apicid_8131_2 = apicid_base + 2;
-	apicid_ck804b = apicid_base + 3;
-}
diff --git a/src/mainboard/tyan/s2895/irq_tables.c b/src/mainboard/tyan/s2895/irq_tables.c
deleted file mode 100644
index 797220ea39..0000000000
--- a/src/mainboard/tyan/s2895/irq_tables.c
+++ /dev/null
@@ -1,175 +0,0 @@
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
-		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
-		uint8_t slot, uint8_t rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-		pirq_info->irq[0].link = link0;
-		pirq_info->irq[0].bitmap = bitmap0;
-		pirq_info->irq[1].link = link1;
-		pirq_info->irq[1].bitmap = bitmap1;
-		pirq_info->irq[2].link = link2;
-		pirq_info->irq[2].bitmap = bitmap2;
-		pirq_info->irq[3].link = link3;
-		pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-extern  unsigned char bus_ck804_0; //1
-extern  unsigned char bus_ck804_1; //2
-extern  unsigned char bus_ck804_2; //3
-extern  unsigned char bus_ck804_3; //4
-extern  unsigned char bus_ck804_4; //5
-extern  unsigned char bus_ck804_5; //6
-extern  unsigned char bus_8131_0;  //7
-extern  unsigned char bus_8131_1;  //8
-extern  unsigned char bus_8131_2;  //9
-extern  unsigned char bus_ck804b_0;//a
-extern  unsigned char bus_ck804b_1;//b
-extern  unsigned char bus_ck804b_2;//c
-extern  unsigned char bus_ck804b_3;//d
-extern  unsigned char bus_ck804b_4;//e
-extern  unsigned char bus_ck804b_5;//f
-
-
-extern  unsigned sbdn3;
-extern  unsigned sbdnb;
-
-
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	unsigned slot_num;
-	uint8_t *v;
-	unsigned sbdn;
-
-	uint8_t sum=0;
-	int i;
-
-	get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
-	sbdn = sysconf.sbdn;
-
-	/* Align the table to be 16 byte aligned. */
-	addr += 15;
-	addr &= ~15;
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (uint8_t *)(addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version  = PIRQ_VERSION;
-
-	pirq->rtr_bus = bus_ck804_0;
-	pirq->rtr_devfn = ((sbdn+9)<<3)|0;
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x10de;
-	pirq->rtr_device = 0x005c;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *) ( &pirq->checksum + 1);
-	slot_num = 0;
-//pci bridge
-	write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-	pirq_info++; slot_num++;
-//pcix bridge
-	write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-	pirq_info++; slot_num++;
-
-	if(sysconf.pci1234[2] & 0xf) {
-	//second pci bridge
-		write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
-		pirq_info++; slot_num++;
-	}
-#if 0
-//smbus
-	write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-
-//usb
-	write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-
-//audio
-	write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-//sata
-	write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-//sata
-	write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-//nic
-	write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-
-//Slot1 PCIE x16
-	write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
-	pirq_info++; slot_num++;
-
-//firewire
-	write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-
-//Slot2 pci
-	write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
-	pirq_info++; slot_num++;
-//nic
-	write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-//Slot3 PCIE x16
-	write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
-	pirq_info++; slot_num++;
-
-//Slot4 PCIX
-	write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
-	pirq_info++; slot_num++;
-
-//Slot5 PCIX
-	write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
-	pirq_info++; slot_num++;
-
-//onboard scsi
-	write_pirq_info(pirq_info, bus_8131_2, (6<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-
-//Slot6 PCIX
-	write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
-	pirq_info++; slot_num++;
-#endif
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "done.\n");
-
-	return	(unsigned long) pirq_info;
-
-}
diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c
deleted file mode 100644
index e62b95ec8f..0000000000
--- a/src/mainboard/tyan/s2895/mainboard.c
+++ /dev/null
@@ -1,22 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/acpi.h>
-#include <cpu/amd/powernow.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern u16 pm_base;
-
-static void mainboard_acpi_fill_ssdt_generator(device_t device) {
-	amd_generate_powernow(0, 0, 0);
-}
-
-static void mainboard_enable(device_t dev)
-{
-	dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator;
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c
deleted file mode 100644
index 1abab1bfc1..0000000000
--- a/src/mainboard/tyan/s2895/mptable.c
+++ /dev/null
@@ -1,200 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern  unsigned char bus_ck804_0; //1
-extern  unsigned char bus_ck804_1; //2
-extern  unsigned char bus_ck804_2; //3
-extern  unsigned char bus_ck804_3; //4
-extern  unsigned char bus_ck804_4; //5
-extern  unsigned char bus_ck804_5; //6
-extern  unsigned char bus_8131_0;  //7
-extern  unsigned char bus_8131_1;  //8
-extern  unsigned char bus_8131_2;  //9
-extern  unsigned char bus_ck804b_0;//a
-extern  unsigned char bus_ck804b_1;//b
-extern  unsigned char bus_ck804b_2;//c
-extern  unsigned char bus_ck804b_3;//d
-extern  unsigned char bus_ck804b_4;//e
-extern  unsigned char bus_ck804b_5;//f
-extern  unsigned apicid_ck804;
-extern  unsigned apicid_8131_1;
-extern  unsigned apicid_8131_2;
-extern  unsigned apicid_ck804b;
-
-extern  unsigned sbdn3;
-extern  unsigned sbdnb;
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	unsigned sbdn;
-	int i, bus_isa;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-
-	get_bus_conf();
-	sbdn = sysconf.sbdn;
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs:	APIC ID	Version	State		Address*/
-	{
-		device_t dev;
-		struct resource *res;
-		uint32_t dword;
-
-		dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
-		if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_1);
-			if (res) {
-				smp_write_ioapic(mc, apicid_ck804, 0x11,
-						 res2mmio(res, 0, 0));
-			}
-
-	/* Initialize interrupt mapping*/
-
-			dword = 0x0120d218;
-			pci_write_config32(dev, 0x7c, dword);
-
-			dword = 0x12008a00;
-			pci_write_config32(dev, 0x80, dword);
-
-			dword = 0x00080d7d;
-			pci_write_config32(dev, 0x84, dword);
-
-		}
-
-		dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
-		if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_0);
-			if (res) {
-				smp_write_ioapic(mc, apicid_8131_1, 0x11,
-						 res2mmio(res, 0, 0));
-			}
-		}
-		dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
-		if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_0);
-			if (res) {
-				smp_write_ioapic(mc, apicid_8131_2, 0x11,
-						 res2mmio(res, 0, 0));
-			}
-		}
-
-	    if(sysconf.pci1234[2] & 0xf) {
-		dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
-		if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_1);
-			if (res) {
-				smp_write_ioapic(mc, apicid_ck804b, 0x11,
-						 res2mmio(res, 0, 0));
-			}
-
-			dword = 0x0000d218; // Why does the factory BIOS have 0?
-			pci_write_config32(dev, 0x7c, dword);
-
-			dword = 0x00000000;
-			pci_write_config32(dev, 0x80, dword);
-
-			dword = 0x00000d00; // Same here.
-			pci_write_config32(dev, 0x84, dword);
-
-		}
-	    }
-
-	}
-
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
-
-/*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-// Onboard ck804 smbus
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
-// 10
-
-// Onboard ck804 USB 1.1
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
-
-// Onboard ck804 USB 2
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
-
-// Onboard ck804 Audio
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
-
-// Onboard ck804 SATA 0
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
-
-// Onboard ck804 SATA 1
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
-
-// Onboard ck804 NIC
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
-
-//Slot PCIE x16
-	for(i=0;i<4;i++) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
-	}
-
-//Onboard Firewire
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
-
-//Slot 2 PCI 32
-	for(i=0;i<4;i++) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); //16
-	}
-
-	if(sysconf.pci1234[2] & 0xf) {
-//Onboard ck804b NIC
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
-
-//Slot 3 PCIE x16
-	for(i=0;i<4;i++) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
-	}
-	}
-
-//Channel B of 8131
-
-//Slot 4 PCI-X 100/66
-	for(i=0;i<4;i++) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
-	}
-
-//Slot 5 PCIX 100/66
-	for(i=0;i<4;i++) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
-	}
-
-//OnBoard LSI SCSI
-	for(i=0;i<2;i++) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
-	}
-
-//Channel A of 8131
-
-//Slot 6 PCIX 133/100/66
-	for(i=0;i<4;i++) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
-	}
-
-/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	mptable_lintsrc(mc, bus_isa);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/tyan/s2895/resourcemap.c b/src/mainboard/tyan/s2895/resourcemap.c
deleted file mode 100644
index 8d2088369d..0000000000
--- a/src/mainboard/tyan/s2895/resourcemap.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * Tyan S2895 needs a different resource map
- *
- */
-
-static void setup_mb_resource_map(void)
-{
-	static const unsigned int register_values[] = {
-	/* Careful set limit registers before base registers which contain the enables */
-	/* DRAM Limit i Registers
-	 * F1:0x44 i = 0
-	 * F1:0x4C i = 1
-	 * F1:0x54 i = 2
-	 * F1:0x5C i = 3
-	 * F1:0x64 i = 4
-	 * F1:0x6C i = 5
-	 * F1:0x74 i = 6
-	 * F1:0x7C i = 7
-	 * [ 2: 0] Destination Node ID
-	 *	   000 = Node 0
-	 *	   001 = Node 1
-	 *	   010 = Node 2
-	 *	   011 = Node 3
-	 *	   100 = Node 4
-	 *	   101 = Node 5
-	 *	   110 = Node 6
-	 *	   111 = Node 7
-	 * [ 7: 3] Reserved
-	 * [10: 8] Interleave select
-	 *	   specifies the values of A[14:12] to use with interleave enable.
-	 * [15:11] Reserved
-	 * [31:16] DRAM Limit Address i Bits 39-24
-	 *	   This field defines the upper address bits of a 40 bit  address
-	 *	   that define the end of the DRAM region.
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
-	PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
-	PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
-	PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
-	PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
-	PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
-	PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-	/* DRAM Base i Registers
-	 * F1:0x40 i = 0
-	 * F1:0x48 i = 1
-	 * F1:0x50 i = 2
-	 * F1:0x58 i = 3
-	 * F1:0x60 i = 4
-	 * F1:0x68 i = 5
-	 * F1:0x70 i = 6
-	 * F1:0x78 i = 7
-	 * [ 0: 0] Read Enable
-	 *	   0 = Reads Disabled
-	 *	   1 = Reads Enabled
-	 * [ 1: 1] Write Enable
-	 *	   0 = Writes Disabled
-	 *	   1 = Writes Enabled
-	 * [ 7: 2] Reserved
-	 * [10: 8] Interleave Enable
-	 *	   000 = No interleave
-	 *	   001 = Interleave on A[12] (2 nodes)
-	 *	   010 = reserved
-	 *	   011 = Interleave on A[12] and A[14] (4 nodes)
-	 *	   100 = reserved
-	 *	   101 = reserved
-	 *	   110 = reserved
-	 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
-	 * [15:11] Reserved
-	 * [13:16] DRAM Base Address i Bits 39-24
-	 *	   This field defines the upper address bits of a 40-bit address
-	 *	   that define the start of the DRAM region.
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
-	/* Memory-Mapped I/O Limit i Registers
-	 * F1:0x84 i = 0
-	 * F1:0x8C i = 1
-	 * F1:0x94 i = 2
-	 * F1:0x9C i = 3
-	 * F1:0xA4 i = 4
-	 * F1:0xAC i = 5
-	 * F1:0xB4 i = 6
-	 * F1:0xBC i = 7
-	 * [ 2: 0] Destination Node ID
-	 *	   000 = Node 0
-	 *	   001 = Node 1
-	 *	   010 = Node 2
-	 *	   011 = Node 3
-	 *	   100 = Node 4
-	 *	   101 = Node 5
-	 *	   110 = Node 6
-	 *	   111 = Node 7
-	 * [ 3: 3] Reserved
-	 * [ 5: 4] Destination Link ID
-	 *	   00 = Link 0
-	 *	   01 = Link 1
-	 *	   10 = Link 2
-	 *	   11 = Reserved
-	 * [ 6: 6] Reserved
-	 * [ 7: 7] Non-Posted
-	 *	   0 = CPU writes may be posted
-	 *	   1 = CPU writes must be non-posted
-	 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-	 *	   This field defines the upp adddress bits of a 40-bit address that
-	 *	   defines the end of a memory-mapped I/O region n
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-//	PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
-	/* Memory-Mapped I/O Base i Registers
-	 * F1:0x80 i = 0
-	 * F1:0x88 i = 1
-	 * F1:0x90 i = 2
-	 * F1:0x98 i = 3
-	 * F1:0xA0 i = 4
-	 * F1:0xA8 i = 5
-	 * F1:0xB0 i = 6
-	 * F1:0xB8 i = 7
-	 * [ 0: 0] Read Enable
-	 *	   0 = Reads disabled
-	 *	   1 = Reads Enabled
-	 * [ 1: 1] Write Enable
-	 *	   0 = Writes disabled
-	 *	   1 = Writes Enabled
-	 * [ 2: 2] Cpu Disable
-	 *	   0 = Cpu can use this I/O range
-	 *	   1 = Cpu requests do not use this I/O range
-	 * [ 3: 3] Lock
-	 *	   0 = base/limit registers i are read/write
-	 *	   1 = base/limit registers i are read-only
-	 * [ 7: 4] Reserved
-	 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-	 *	   This field defines the upper address bits of a 40bit address
-	 *	   that defines the start of memory-mapped I/O region i
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-//	PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
-	/* PCI I/O Limit i Registers
-	 * F1:0xC4 i = 0
-	 * F1:0xCC i = 1
-	 * F1:0xD4 i = 2
-	 * F1:0xDC i = 3
-	 * [ 2: 0] Destination Node ID
-	 *	   000 = Node 0
-	 *	   001 = Node 1
-	 *	   010 = Node 2
-	 *	   011 = Node 3
-	 *	   100 = Node 4
-	 *	   101 = Node 5
-	 *	   110 = Node 6
-	 *	   111 = Node 7
-	 * [ 3: 3] Reserved
-	 * [ 5: 4] Destination Link ID
-	 *	   00 = Link 0
-	 *	   01 = Link 1
-	 *	   10 = Link 2
-	 *	   11 = reserved
-	 * [11: 6] Reserved
-	 * [24:12] PCI I/O Limit Address i
-	 *	   This field defines the end of PCI I/O region n
-	 * [31:25] Reserved
-	 */
-	PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
-	PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001, // need to talk to ANALOG of second CK804 to release PCI E reset
-	PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
-	/* PCI I/O Base i Registers
-	 * F1:0xC0 i = 0
-	 * F1:0xC8 i = 1
-	 * F1:0xD0 i = 2
-	 * F1:0xD8 i = 3
-	 * [ 0: 0] Read Enable
-	 *	   0 = Reads Disabled
-	 *	   1 = Reads Enabled
-	 * [ 1: 1] Write Enable
-	 *	   0 = Writes Disabled
-	 *	   1 = Writes Enabled
-	 * [ 3: 2] Reserved
-	 * [ 4: 4] VGA Enable
-	 *	   0 = VGA matches Disabled
-	 *	   1 = matches all address < 64K and where A[9:0] is in the
-	 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
-	 * [ 5: 5] ISA Enable
-	 *	   0 = ISA matches Disabled
-	 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
-	 *	       from matching agains this base/limit pair
-	 * [11: 6] Reserved
-	 * [24:12] PCI I/O Base i
-	 *	   This field defines the start of PCI I/O region n
-	 * [31:25] Reserved
-	 */
-	PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
-	PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033,
-	PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
-	/* Config Base and Limit i Registers
-	 * F1:0xE0 i = 0
-	 * F1:0xE4 i = 1
-	 * F1:0xE8 i = 2
-	 * F1:0xEC i = 3
-	 * [ 0: 0] Read Enable
-	 *	   0 = Reads Disabled
-	 *	   1 = Reads Enabled
-	 * [ 1: 1] Write Enable
-	 *	   0 = Writes Disabled
-	 *	   1 = Writes Enabled
-	 * [ 2: 2] Device Number Compare Enable
-	 *	   0 = The ranges are based on bus number
-	 *	   1 = The ranges are ranges of devices on bus 0
-	 * [ 3: 3] Reserved
-	 * [ 6: 4] Destination Node
-	 *	   000 = Node 0
-	 *	   001 = Node 1
-	 *	   010 = Node 2
-	 *	   011 = Node 3
-	 *	   100 = Node 4
-	 *	   101 = Node 5
-	 *	   110 = Node 6
-	 *	   111 = Node 7
-	 * [ 7: 7] Reserved
-	 * [ 9: 8] Destination Link
-	 *	   00 = Link 0
-	 *	   01 = Link 1
-	 *	   10 = Link 2
-	 *	   11 - Reserved
-	 * [15:10] Reserved
-	 * [23:16] Bus Number Base i
-	 *	   This field defines the lowest bus number in configuration region i
-	 * [31:24] Bus Number Limit i
-	 *	   This field defines the highest bus number in configuration region i
-	 */
-	PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
-	PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 	*/
-	PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013, /* link 0 of cpu 1 --> Nvidia CK 804 Slave 	*/
-	PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, /*113 link 1 of cpu 1 --> HT connector */
-	};
-	int max;
-	max = ARRAY_SIZE(register_values);
-	setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c
deleted file mode 100644
index 086df63f04..0000000000
--- a/src/mainboard/tyan/s2895/romstage.c
+++ /dev/null
@@ -1,155 +0,0 @@
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <lib.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include <southbridge/nvidia/ck804/early_smbus.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
-#include <superio/smsc/lpc47b397/lpc47b397.h>
-#include "superio/smsc/lpc47b397/early_gpio.c"
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/mtrr.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-#define SUPERIO_GPIO_IO_BASE 0x400
-
-static void memreset_setup(void) { }
-static void memreset(int controllers, const struct mem_controller *ctrl) { }
-static void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-static void sio_gpio_setup(void)
-{
-	unsigned value;
-
-	/*Enable onboard scsi*/
-	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c,
-	  (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
-	value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
-	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <southbridge/nvidia/ck804/early_setup_ss.h>
-
-//set GPIO to input mode
-#define CK804_MB_SETUP \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
-
-#include "southbridge/nvidia/ck804/early_setup_car.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
-	unsigned value;
-	u32 dword;
-	u8 byte;
-
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
-
-	byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
-	byte |= 0x20;
-	pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<29)|(1<<0);
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
-	dword |= (1<<16);
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
-
-	lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
-	value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
-	value &= 0xbf;
-	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	static const u16 spd_addr [] = {
-		DIMM0, DIMM2, 0, 0,
-		DIMM1, DIMM3, 0, 0,
-		DIMM4, DIMM6, 0, 0,
-		DIMM5, DIMM7, 0, 0,
-	};
-
-	int needs_reset;
-	unsigned bsp_apicid = 0, nodes;
-	struct mem_controller ctrl[8];
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		/* Nothing special needs to be done to find bus 0 */
-		/* Allow the HT devices to be found */
-		enumerate_ht_chain();
-		sio_setup();
-	}
-
-	if (bist == 0)
-		bsp_apicid = init_cpus(cpu_init_detectedx);
-
-	lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	sio_gpio_setup();
-
-	setup_mb_resource_map();
-
-	needs_reset = setup_coherent_ht_domain();
-
-	wait_all_core0_started();
-
-	// It is said that we should start core1 after all core0 launched
-	start_other_cores();
-	wait_all_other_cores_started(bsp_apicid);
-
-	needs_reset |= ht_setup_chains_x();
-	needs_reset |= ck804_early_setup_x();
-	if (needs_reset) {
-		printk(BIOS_INFO, "ht reset -\n");
-		soft_reset();
-	}
-
-	allow_all_aps_stop(bsp_apicid);
-
-	nodes = get_nodes();
-	//It's the time to set ctrl now;
-	fill_mem_ctrl(nodes, ctrl, spd_addr);
-
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(nodes, ctrl);
-
-	post_cache_as_ram();
-}