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authorKane Chen <kane.chen@intel.com>2017-06-01 20:08:48 +0800
committerAaron Durbin <adurbin@chromium.org>2017-06-03 07:18:24 +0200
commit8cb70914cab728ea01f5200d9d90dcb444d14f26 (patch)
treef14a2bf742c3e14aefdb40a8b7632bc0b777d977
parent4db78e39dafa78a65ca9794e9344ce99f699740a (diff)
downloadcoreboot-8cb70914cab728ea01f5200d9d90dcb444d14f26.tar.xz
mb/google/fizz: set SD_CDZ to edge trigger.
This is to align with the SD_CD GpioInt setting in acpi BUG=b:62067569 TEST=checked unused interrupt on SD_CD does not happen after s3 resume Change-Id: I40aefcb0f571e7f6773a6d20226f357707aa041a Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/20001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/mainboard/google/fizz/gpio.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h
index 07d9281e75..ced33e97b0 100644
--- a/src/mainboard/google/fizz/gpio.h
+++ b/src/mainboard/google/fizz/gpio.h
@@ -42,7 +42,8 @@ static const struct pad_config gpio_table[] = {
/* ESPI_IO3 */
/* ESPI_CS# */
/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */
-/* PIRQA# */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP), /* SD_CDZ */
+/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP,
+ EDGE), /* SD_CDZ */
/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */
/* ESPI_CLK */
/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */