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authorSubrata Banik <subrata.banik@intel.com>2019-09-11 10:32:31 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-09-12 13:16:46 +0000
commit8cced29eed33285e0a086231c567f4633372f004 (patch)
treebbeb0fb7e11c76f0ef9a8fe2b3e70663ab3d66d5
parentd589c8681ebaa9b45168a23c8d3fe522e776b0f4 (diff)
downloadcoreboot-8cced29eed33285e0a086231c567f4633372f004.tar.xz
soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usage
PchPwrOptEnable FSP UPD is for internal testing and not really available in externally released FSP source hence assigning this UPD using devicetree config dmipwroptimize doesn't do anything. TEST=Build and boot sarien/arcada. Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
-rw-r--r--src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb1
-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb1
-rw-r--r--src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb1
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb1
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb1
-rw-r--r--src/soc/intel/cannonlake/chip.h3
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c1
7 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb
index 3628264f8a..7050b1ef6e 100644
--- a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb
@@ -32,7 +32,6 @@ chip soc/intel/cannonlake
register "psys_pmax" = "140"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
- register "dmipwroptimize" = "1"
register "satapwroptimize" = "1"
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51"
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index d8ef7a9d2f..d824a552d0 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -32,7 +32,6 @@ chip soc/intel/cannonlake
register "psys_pmax" = "140"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
- register "dmipwroptimize" = "1"
register "satapwroptimize" = "1"
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51"
diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb
index 84aacd58ec..f2367ffa1d 100644
--- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb
@@ -34,7 +34,6 @@ chip soc/intel/cannonlake
register "speed_shift_enable" = "1"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
- register "dmipwroptimize" = "1"
register "satapwroptimize" = "1"
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRateForIa" = "2"
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index ebcf140b4c..0f3023cace 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -32,7 +32,6 @@ chip soc/intel/cannonlake
register "psys_pmax" = "140"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
- register "dmipwroptimize" = "1"
register "satapwroptimize" = "1"
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index d3aab62a68..cd216e593b 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -34,7 +34,6 @@ chip soc/intel/cannonlake
register "speed_shift_enable" = "1"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
- register "dmipwroptimize" = "1"
register "satapwroptimize" = "1"
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRateForIa" = "2"
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 9c7c17147e..451c920fae 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -387,9 +387,6 @@ struct soc_intel_cannonlake_config {
uint8_t SlowSlewRateForSa;
uint8_t SlowSlewRateForFivr;
- /* DMI Power Optimizer */
- uint8_t dmipwroptimize;
-
/* SATA Power Optimizer */
uint8_t satapwroptimize;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index f48a626be9..76d40aa624 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -377,7 +377,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr;
/* Power Optimizer */
- params->PchPwrOptEnable = config->dmipwroptimize;
params->SataPwrOptEnable = config->satapwroptimize;
/* Disable PCH ACPI timer */