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authorFrans Hendriks <fhendriks@eltan.com>2019-03-04 15:43:47 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-03-06 20:06:02 +0000
commit912616941930a352c27a841a735476998e804829 (patch)
treeb192efde24751ee43c1ce6618e304f10836e6168
parentb063cbeffe882c496b4411e5caeb478a9a1d002f (diff)
downloadcoreboot-912616941930a352c27a841a735476998e804829.tar.xz
soc/intel/braswell/include/soc/spi.h: Add OPTYPE values
Add SPI_OPTYPE_XXX values for the SPI controller. BUG=N/A TEST=flashrom on Facebook FBG-1701 Change-Id: Id183d68b3a80b2e7ab1a0685580d79ca327db03a Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
-rw-r--r--src/soc/intel/braswell/include/soc/spi.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h
index 49f3fcc0ac..2d275450fa 100644
--- a/src/soc/intel/braswell/include/soc/spi.h
+++ b/src/soc/intel/braswell/include/soc/spi.h
@@ -3,6 +3,7 @@
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2019 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -31,6 +32,10 @@
# define DATA_CYCLE (0x1 << 14)
#define PREOP 0x94
#define OPTYPE 0x96
+# define SPI_OPTYPE_RD_NOADDR 0x00 /* Read, no address */
+# define SPI_OPTYPE_WR_NOADDR 0x01 /* Write, no address */
+# define SPI_OPTYPE_RD_ADDR 0x02 /* Read, address required */
+# define SPI_OPTYPE_WR_ADDR 0x03 /* Write, address required */
#define OPMENU0 0x98
#define OPMENU1 0x9c
#define LVSCC 0xc4