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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2019-09-04 16:14:10 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-09-05 14:59:38 +0000
commit940fb57c06ff706f8e3ab16451548ab93aff1340 (patch)
tree4e6af04302ad8d5cd93e27225a2bfab2b1f7481b
parentb89ce2e1b4989557ba70780ceae165734fb17622 (diff)
downloadcoreboot-940fb57c06ff706f8e3ab16451548ab93aff1340.tar.xz
mb/google/drallion: modify PCIE setting
Based on HW schematic to modify PCIE setting. BUG=b:138082886 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia744a6f3cba76c507c1c43b0a981cb6d89c1a40f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb31
1 files changed, 18 insertions, 13 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 8870126759..561217a76a 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -189,22 +189,27 @@ chip soc/intel/cannonlake
},
}"
+ # PCIe port 9 for Card Reader
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieClkSrcUsage[4]" = "8"
+ register "PcieClkSrcClkReq[4]" = "4"
+
# PCIe port 10 for M.2 2230 WLAN
register "PcieRpEnable[9]" = "1"
- register "PcieClkSrcUsage[2]" = "9"
- register "PcieClkSrcClkReq[2]" = "2"
-
- # PCIe port 11 for card reader
- register "PcieRpEnable[10]" = "1"
- register "PcieRpLtrEnable[10]" = "1"
- register "PcieClkSrcUsage[1]" = "10"
+ register "PcieClkSrcUsage[1]" = "9"
register "PcieClkSrcClkReq[1]" = "1"
+ # PCIe port 12 for M.2 3042 WWAN
+ register "PcieRpEnable[11]" = "1"
+ register "PcieClkSrcUsage[0]" = "11"
+ register "PcieClkSrcClkReq[0]" = "0"
+
# PCIe port 13 for M.2 2280 SSD
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
- register "PcieClkSrcUsage[4]" = "12"
- register "PcieClkSrcClkReq[4]" = "4"
+ register "PcieClkSrcUsage[2]" = "12"
+ register "PcieClkSrcClkReq[2]" = "2"
# GPIO PM programming
register "gpio_override_pm" = "1"
@@ -359,7 +364,7 @@ chip soc/intel/cannonlake
end
end # I2C #4
device pci 19.1 off end # I2C #5
- device pci 19.2 off end # UART #2
+ device pci 19.2 on end # UART #2
device pci 1a.0 off end # eMMC
device pci 1c.0 off end # PCI Express Port 1 (USB)
device pci 1c.1 off end # PCI Express Port 2 (USB)
@@ -373,12 +378,12 @@ chip soc/intel/cannonlake
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
end # PCI Express Port 9
device pci 1d.1 on end # PCI Express Port 10
- device pci 1d.2 on end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 on end # PCI Express Port 12
device pci 1d.4 on
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
end # PCI Express Port 13 (x4)
- device pci 1e.0 on end # UART #0
+ device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1