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authorKarthikeyan Ramasubramanian <kramasub@google.com>2020-02-07 17:37:17 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-02-17 15:36:07 +0000
commit95ea799019fdb7c0baee70bd07196910dbc0cd95 (patch)
treeb8ee169779a55b4e2c55f8e24026c5c74903a80e
parent2a3cef29d81ab9200b8226be41a09f975c9ed485 (diff)
downloadcoreboot-95ea799019fdb7c0baee70bd07196910dbc0cd95.tar.xz
mb/google/dedede: Add console UART configuration
Enable UART Port 2 as console UART and configure the concerned GPIOs. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I30a64a3c96226ce3244d55919b6d65fbf0a096e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38776 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/dedede/Kconfig1
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/devicetree.cb4
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/gpio.c9
3 files changed, 12 insertions, 2 deletions
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 9b5bd4af5e..c2f66a43eb 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE
select EC_GOOGLE_CHROMEEC_ESPI
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
+ select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index e98b686608..4b2a3c5b13 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -49,7 +49,7 @@ chip soc/intel/tigerlake
register "SerialIoUartMode" = "{
[PchSerialIoIndexUART0] = PchSerialIoDisabled,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
- [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoSkipInit,
}"
# Intel Common SoC Config
@@ -91,7 +91,7 @@ chip soc/intel/tigerlake
device pci 17.0 off end # SATA
device pci 19.0 off end # I2C 4
device pci 19.1 off end # I2C 5
- device pci 19.2 off end # UART 2
+ device pci 19.2 on end # UART 2
device pci 1a.0 off end # eMMC
device pci 1c.0 off end # PCI Express Root Port 1
device pci 1c.1 off end # PCI Express Root Port 2
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c
index b9d77bf585..c334f1107a 100644
--- a/src/mainboard/google/dedede/variants/baseboard/gpio.c
+++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c
@@ -32,6 +32,15 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* B18 : H1_SLAVE_SPI_MOSI_R */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+
+ /* C20 : UART_DBG_TX_AP_RX */
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+ /* C21 : UART_AP_TX_DBG_RX */
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+ /* C22 : UART2_RTS_N */
+ PAD_NC(GPP_C22, DN_20K),
+ /* C23 : UART2_CTS_N */
+ PAD_NC(GPP_C23, DN_20K),
};
/* Early pad configuration in bootblock */