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authorArthur Heymans <arthur@aheymans.xyz>2018-05-15 16:45:21 +0200
committerArthur Heymans <arthur@aheymans.xyz>2019-05-27 17:25:57 +0000
commit97c7c6bbb6c9dd2ef4f917c3c4c16a8ff0de5d9f (patch)
tree30a67e32ce77415b5b4f8734029a2037e4a7a6d5
parentb66ee5507c4c2395868a5cd350dc8a7eb46542fd (diff)
downloadcoreboot-97c7c6bbb6c9dd2ef4f917c3c4c16a8ff0de5d9f.tar.xz
cpu/intel/model_2065x: Put stage cache in TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
-rw-r--r--src/cpu/intel/model_2065x/Kconfig5
-rw-r--r--src/cpu/intel/model_2065x/Makefile.inc4
-rw-r--r--src/cpu/intel/model_2065x/model_2065x.h18
-rw-r--r--src/cpu/intel/model_2065x/stage_cache.c30
-rw-r--r--src/northbridge/intel/nehalem/northbridge.c7
-rw-r--r--src/northbridge/intel/nehalem/ram_calc.c6
6 files changed, 63 insertions, 7 deletions
diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index 707713c697..d8c016867c 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -21,6 +21,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON
select NO_FIXED_XIP_ROM_SIZE
select PARALLEL_MP
+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config BOOTBLOCK_CPU_INIT
string
@@ -30,4 +31,8 @@ config SMM_TSEG_SIZE
hex
default 0x800000
+config SMM_RESERVED_SIZE
+ hex
+ default 0x100000
+
endif
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 043141ac18..39246c0708 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -19,6 +19,10 @@ ramstage-y += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+romstage-y += stage_cache.c
+ramstage-y += stage_cache.c
+postcar-y += stage_cache.c
+
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index 904e794219..e7ba2a771b 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -80,4 +80,22 @@ void set_power_limits(u8 power_limit_1_time);
int cpu_config_tdp_levels(void);
#endif
+/*
+ * Region of SMM space is reserved for multipurpose use. It falls below
+ * the IED region and above the SMM handler.
+ */
+#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
+#define RESERVED_SMM_OFFSET (CONFIG_SMM_TSEG_SIZE - RESERVED_SMM_SIZE)
+
+/* Sanity check config options. */
+#if (CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE)
+# error "CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE"
+#endif
+#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
+# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
+#endif
+#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)
+# error "CONFIG_SMM_TSEG_SIZE is not a power of 2"
+#endif
+
#endif
diff --git a/src/cpu/intel/model_2065x/stage_cache.c b/src/cpu/intel/model_2065x/stage_cache.c
new file mode 100644
index 0000000000..ab8ac979c1
--- /dev/null
+++ b/src/cpu/intel/model_2065x/stage_cache.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <stage_cache.h>
+#include <cpu/intel/smm/gen1/smi.h>
+#include "model_2065x.h"
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+ /*
+ * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+ * The top of RAM is defined to be the TSEG base address.
+ */
+ *size = RESERVED_SMM_SIZE;
+ *base = (void *)((uintptr_t)northbridge_get_tseg_base()
+ + RESERVED_SMM_OFFSET);
+}
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 233b0bbd00..485cb27f45 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -171,13 +171,6 @@ static void mc_read_resources(struct device *dev)
add_fixed_resources(dev, 10);
}
-u32 northbridge_get_tseg_base(void)
-{
- struct device *dev = pcidev_on_root(0, 0);
-
- return pci_read_config32(dev, TSEG) & ~1;
-}
-
u32 northbridge_get_tseg_size(void)
{
return CONFIG_SMM_TSEG_SIZE;
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index 163f21ce3c..ca821da2dc 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -23,6 +23,7 @@
#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h>
#include <program_loading.h>
+#include <cpu/intel/smm/gen1/smi.h>
#include "nehalem.h"
static uintptr_t smm_region_start(void)
@@ -32,6 +33,11 @@ static uintptr_t smm_region_start(void)
return tom;
}
+u32 northbridge_get_tseg_base(void)
+{
+ return (u32)smm_region_start & ~1;
+}
+
void *cbmem_top(void)
{
return (void *) smm_region_start();