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authorPaul Menzel <pmenzel@molgen.mpg.de>2020-03-11 20:05:52 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-15 12:56:48 +0000
commit9f111859207faf24406dab335eb1192960e200f9 (patch)
tree967cfa1687f0d612d0b443908b995c1e02317a07
parent655dba40559e79fcac520a51819d10cd58c25adf (diff)
downloadcoreboot-9f111859207faf24406dab335eb1192960e200f9.tar.xz
soc/intel/icelake: Correct past participle in comment
Change-Id: I117c8d2f71824292c4ca87b6f9434d2106bb512d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/soc/intel/icelake/romstage/fsp_params.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c
index 8dd6bfdcf7..99f606b4e2 100644
--- a/src/soc/intel/icelake/romstage/fsp_params.c
+++ b/src/soc/intel/icelake/romstage/fsp_params.c
@@ -32,7 +32,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
if (!dev || !dev->enabled) {
/*
* Skip IGD initialization in FSP if device
- * is disable in devicetree.cb.
+ * is disabled in devicetree.cb.
*/
m_cfg->InternalGfx = 0;
m_cfg->IgdDvmt50PreAlloc = 0;