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authorNico Huber <nico.h@gmx.de>2019-12-31 15:52:14 +0100
committerMatt DeVillier <matt.devillier@gmail.com>2020-01-07 18:25:04 +0000
commita0259b427345824abf6b7d80fe66415b47b1cc73 (patch)
tree00f2ca1b4d9d872f6710853ef0e372333608cd33
parent73be5f7211554d6698841e89794a695a80fa362c (diff)
downloadcoreboot-a0259b427345824abf6b7d80fe66415b47b1cc73.tar.xz
mb/google/{beltino,jecht}: Drop SIO configuration lines
These are meaningless for boards without SIO devices. Change-Id: I252bba6ff1a2547fd0661ad3076470376e95bdd6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
-rw-r--r--src/mainboard/google/beltino/devicetree.cb4
-rw-r--r--src/mainboard/google/jecht/devicetree.cb4
2 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb
index 89758dd1f5..f4c9e850ab 100644
--- a/src/mainboard/google/beltino/devicetree.cb
+++ b/src/mainboard/google/beltino/devicetree.cb
@@ -55,10 +55,6 @@ chip northbridge/intel/haswell
register "sata_port_map" = "0x1"
register "sata_devslp_disable" = "0x1"
- register "sio_acpi_mode" = "0"
- register "sio_i2c0_voltage" = "0" # 3.3V
- register "sio_i2c1_voltage" = "0" # 3.3V
-
# Force enable ASPM for PCIe Port 4
register "pcie_port_force_aspm" = "0x10"
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb
index d34bf7a5d5..19d0c48e07 100644
--- a/src/mainboard/google/jecht/devicetree.cb
+++ b/src/mainboard/google/jecht/devicetree.cb
@@ -30,10 +30,6 @@ chip soc/intel/broadwell
register "sata_port_map" = "0x1"
register "sata_devslp_disable" = "0x1"
- register "sio_acpi_mode" = "0"
- register "sio_i2c0_voltage" = "0" # 3.3V
- register "sio_i2c1_voltage" = "0" # 3.3V
-
# Force enable ASPM for PCIe Port 4
register "pcie_port_force_aspm" = "0x10"