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authorSubrata Banik <subrata.banik@intel.com>2019-06-04 14:16:02 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-06-13 04:38:39 +0000
commita0368a0950bbd346b816c4397cfe9e86617d4f77 (patch)
treea3b0a568181f2e03a72fa3cce46683824cff4982
parent3d152ac388fa43b4c3d1bfeedcb6a40f1479ace3 (diff)
downloadcoreboot-a0368a0950bbd346b816c4397cfe9e86617d4f77.tar.xz
soc/intel/{cml, whl}: Add option to skip HECI disable in SMM
This patch provides an additional option to skip HECI function disabling using SMM mode for WHL and CML platform, where FSP has dedicated UPD to make HECI function disable. User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated UPD. Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig to make HECI disable and WHL/CML has to rely on FSP to make HECI disable. Change-Id: If3b064f3c32877235916f966a01beb525156d188 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
-rw-r--r--src/soc/intel/cannonlake/Kconfig1
-rw-r--r--src/soc/intel/cannonlake/smihandler.c2
-rw-r--r--src/soc/intel/common/block/smm/Kconfig8
-rw-r--r--src/soc/intel/icelake/Kconfig1
-rw-r--r--src/soc/intel/icelake/smihandler.c2
5 files changed, 12 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 76906b2548..dac3522d0a 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -107,6 +107,7 @@ config CPU_SPECIFIC_OPTIONS
select UDK_2017_BINDING
select DISPLAY_FSP_VERSION_INFO
select FSP_T_XIP if FSP_CAR
+ select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE
config DCACHE_RAM_BASE
default 0xfef00000
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index 9af291700b..e8f0d17833 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -88,7 +88,7 @@ void smihandler_soc_at_finalize(void)
config = dev->chip_info;
- if (config->HeciEnabled == 0)
+ if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
pch_disable_heci();
}
diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig
index a58c63102d..ab5ee03a6d 100644
--- a/src/soc/intel/common/block/smm/Kconfig
+++ b/src/soc/intel/common/block/smm/Kconfig
@@ -23,3 +23,11 @@ config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS
Time in milliseconds that SLP_SMI for S5 waits for before
enabling sleep. This is required to avoid any race between
SLP_SMI and PWRBTN SMI.
+
+config HECI_DISABLE_USING_SMM
+ bool
+ depends on SOC_INTEL_COMMON_BLOCK_SMM
+ default n
+ help
+ HECI disable using SMM. Select this option to make HECI disable
+ using SMM mode, independent of dedicated UPD to perform HECI disable.
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 052e37dadb..f0b291877d 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -62,6 +62,7 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC
select UDK_2017_BINDING
select DISPLAY_FSP_VERSION_INFO
+ select HECI_DISABLE_USING_SMM
config DCACHE_RAM_BASE
default 0xfef00000
diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c
index 5c00b63720..5fb2480604 100644
--- a/src/soc/intel/icelake/smihandler.c
+++ b/src/soc/intel/icelake/smihandler.c
@@ -86,7 +86,7 @@ void smihandler_soc_at_finalize(void)
config = dev->chip_info;
- if (config->HeciEnabled == 0)
+ if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
pch_disable_heci();
}