summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMatt DeVillier <matt.devillier@gmail.com>2018-01-21 18:32:07 -0600
committerMatt DeVillier <matt.devillier@gmail.com>2020-04-03 16:24:17 +0000
commita2804781feaa7ba7db198fa03f20be861ccbe4a3 (patch)
tree9a51f141132eb0805667c05a8a24908f4793a564
parent8fbfcc3a06d2dde8aa625db123b42cfe29aa0752 (diff)
downloadcoreboot-a2804781feaa7ba7db198fa03f20be861ccbe4a3.tar.xz
mb/google/cyan: Switch eMMC and SD from ACPI to PCI mode
Braswell boards don't work well with the eMMC and SD controller in ACPI in payloads other than depthcharge - SeaBIOS requires an onerous workaround (manually determining the PCI BAR0 address for each eMMC and SD controller, then adding adding etc/sdcard entries to the CBFS), and Tianocore can't see the devices at all. To make the common use-case work better, switch to PCI mode. Test: build/boot cyan variants with SeaBIOS and Tianocore payloads, verify eMMC and SD card visible and bootable to both payloads and OSes. Change-Id: I71947603e22a37fe2c8ef4eaac8a3aa0d0ed1cec Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40002 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/cyan/devicetree.cb10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb
index 328a60817e..b13f3f9e90 100644
--- a/src/mainboard/google/cyan/devicetree.cb
+++ b/src/mainboard/google/cyan/devicetree.cb
@@ -19,7 +19,7 @@ chip soc/intel/braswell
# Set the parameters for SiliconInit
############################################################
- register "PcdSdcardMode" = "PCH_ACPI_MODE"
+ register "PcdSdcardMode" = "PCH_PCI_MODE"
register "PcdEnableHsuart0" = "0"
register "PcdEnableHsuart1" = "1"
register "PcdEnableAzalia" = "1"
@@ -36,7 +36,7 @@ chip soc/intel/braswell
register "PcdEnableI2C6" = "0"
register "PunitPwrConfigDisable" = "0" # Enable SVID
register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
- register "PcdEmmcMode" = "PCH_ACPI_MODE"
+ register "PcdEmmcMode" = "PCH_PCI_MODE"
register "PcdUsb3ClkSsc" = "1"
register "PcdDispClkSsc" = "1"
register "PcdSataClkSsc" = "1"
@@ -84,10 +84,10 @@ chip soc/intel/braswell
# LPE audio codec settings
register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
- # Enable devices in ACPI mode
+ # Enable LPSS and LPE devices in ACPI mode
register "lpss_acpi_mode" = "1"
- register "emmc_acpi_mode" = "1"
- register "sd_acpi_mode" = "1"
+ register "emmc_acpi_mode" = "0"
+ register "sd_acpi_mode" = "0"
register "lpe_acpi_mode" = "1"
# Disable SLP_X stretching after SUS power well fail.