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authorJames Ye <jye836@gmail.com>2019-01-19 18:25:04 +1100
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2019-01-25 12:44:43 +0000
commita6450d7b761ea62201d83a99584e84d754e667b8 (patch)
tree5e473c5a246fa3f751910142006f64f7c84741f7
parent769c309e3df8c4e53a98a2ded6fc85843fea1829 (diff)
downloadcoreboot-a6450d7b761ea62201d83a99584e84d754e667b8.tar.xz
mb/lenovo/x131e: remove PMH7
This board does not have PMH7. Change-Id: I382958f012e5f4445efc76c7f36bbdf460c29be4 Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/31065 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/lenovo/x131e/Kconfig1
-rw-r--r--src/mainboard/lenovo/x131e/devicetree.cb8
2 files changed, 1 insertions, 8 deletions
diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig
index f52978fe3b..2f936a915d 100644
--- a/src/mainboard/lenovo/x131e/Kconfig
+++ b/src/mainboard/lenovo/x131e/Kconfig
@@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select USE_NATIVE_RAMINIT
select SOUTHBRIDGE_INTEL_C216
- select EC_LENOVO_PMH7
select EC_LENOVO_H8
select NO_UART_ON_SUPERIO
select BOARD_ROMSIZE_KB_12288
diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb
index 589c6c9fb9..21d38f5ab2 100644
--- a/src/mainboard/lenovo/x131e/devicetree.cb
+++ b/src/mainboard/lenovo/x131e/devicetree.cb
@@ -90,18 +90,12 @@ chip northbridge/intel/sandybridge
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge PCI-LPC bridge
- chip ec/lenovo/pmh7
- register "backlight_enable" = "0x01"
- register "dock_event_enable" = "0x00"
- device pnp ff.1 on end # dummy
- end
-
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/lenovo/h8
- device pnp ff.2 on # dummy
+ device pnp ff.1 on # dummy
io 0x60 = 0x62
io 0x62 = 0x66
io 0x64 = 0x1600